8042 - Keyboard Controller (AT,PS/2)

8042 Commands & Responses - (Port 60h)

Commands System Issues to Keyboard (write port 60h)

Command	Description
EDh	Set/Reset Mode Indicators, keyboard responds with ACK then waits for a following option byte. When the option byte is received the keyboard again ACK's and then sets the LED's accordingly. Scanning is resumed if scanning was enabled. If another command is received instead of the option byte (high bit set on) this command is terminated. Hardware defaults to these indicators turned off. \|7-3\|2\|1\|0\| Keyboard Status Indicator Option Byte \| \| \| `--- Scroll-Lock indicator (0=off, 1=on) \| \| `---- Num-Lock indicator (0=off, 1=on) \| `----- Caps-Lock indicator (0=off, 1=on) `------- reserved (must be zero)
EEh	Diagnostic Echo, keyboard echoes the EE byte back to the system without an acknowledgement.
F0h	PS/2 Select/Read Alternate Scan Code Sets, instructs keyboard to use one of the three make/break scan code sets. Keyboard responds by clearing the output buffer/typematic key and then transmits an ACK. The system must follow up by sending an option byte which will again be ACK'ed by the keyboard: 00 return byte indicating scan code set in use 01 select scan code set 1 (used on PC & XT) 02 select scan code set 2 03 select scan code set 3
F2h	PS/2 Read Keyboard ID, keyboard responds with an ACK and a two byte keyboard ID of 83AB.
F3h	Set Typematic Rate/Delay, keyboard responds with ACK and waits for rate/delay byte. Upon receipt of the rate/delay byte the keyboard responds with an ACK, then sets the new typematic values and scanning continues if scanning was enabled. \|7\|6\|5\|4\|3\|2\|1\|0\| Typematic Rate/Delay Option Byte \| \| \| \|-+-+-+-+---- typematic rate indicator (see INT 16,3) \| \| `------- A in period formula (see below) \| \| \| `---------- B is period formula (see below) \| `------------- typematic delay `-------------- always zero delay = (rate+1) * 250 (in milliseconds) rate = (8+A) * (2*B) 4.17 (in seconds, +/- 20%) Defaults to 10.9 characters per second and a 500ms delay. If a command byte (byte with high bit set) is received instead of an option byte this command is cancelled.
F4h	Enable Keyboard, cause the keyboard to clear its output buffer and last typematic key and then respond with an ACK. The keyboard then begins scanning.
F5h	Default w/Disable, resets keyboard to power-on condition by clearing the output buffer, resetting typematic rate/delay, resetting last typematic key and setting default key types. The keyboard responds with an ACK and waits for the next instruction.
F6h	Set Default, resets to power-on condition by clearing the output buffer, resetting typematic rate/delay and last typematic key and sets default key types. The keyboard responds with an ACK and continues scanning.
F7h	PS/2 Set All Keys to Typematic, keyboard responds by sending an ACK, clearing its output buffer and setting the key type to Typematic. Scanning continues if scanning was enabled. This command may be sent while using any Scan Code Set but only has effect when Scan Code Set 3 is in use.
F8h	PS/2 Set All Keys to Make/Break, keyboard responds by sending an ACK, clearing its output buffer and setting the key type to Make/Break. Scanning continues if scanning was enabled. This command may be sent while using any Scan Code Set but only has effect when Scan Code Set 3 is in use.
F9h	PS/2 Set All Keys to Make, keyboard responds by sending an ACK, clearing its output buffer and setting the key type to Make. Scanning continues if scanning was enabled. This command may be sent while using any Scan Code Set but only has effect when Scan Code Set 3 is in use.
FAh	PS/2 Set All Keys to Typematic Make/Break, keyboard responds by sending an ACK, clearing its output buffer and setting the key type to Typematic Make/Break. Scanning continues if scanning was enabled. This command may be sent while using any Scan Code Set but only has effect when Scan Code Set 3 is in use.
FBh	PS/2 Set Key Type to Typematic, keyboard responds by sending an ACK, clearing its output buffer and then waiting for the key ID (make code from Scan Code Set 3). The specified key type is then set to typematic.This command may be sent while using any Scan Code Set but only has effect when Scan Code Set 3 is in use.
FCh	PS/2 Set Key Type to Make/Break, keyboard responds by sending an ACK, clearing its output buffer and then waiting for the key ID (make code from Scan Code Set 3). The specified key type is then set to Make/Break. This command may be sent while using any Scan Code Set but only has effect when Scan Code Set 3 is in use.
FDh	PS/2 Set Key Type to Make, keyboard responds by sending an ACK, clearing its output buffer and then waiting for the key ID (make code from Scan Code Set 3). The specified key type is then set to Make. This command may be sent while using any Scan Code Set but only has effect when Scan Code Set 3 is in use.
FEh	Resend, should be sent when a transmission error is detected from the keyboard
FFh	Reset, Keyboard sends ACK and waits for system to receive it then begins a program reset and Basic Assurance Test (BAT). Keyboard returns a one byte completion code then sets default Scan Code Set 2.

Keyboard Responses to System (read port 60h)

00h	Key Detection Error or Overrun Error for Scan Code Set 1, replaces last key in the keyboard buffer if the buffer is full.
AAh	BAT Completion Code, keyboard sends this to indicate the keyboard test was successful.
EEh	Echo Response, response to the Echo command.
F0h	Break Code Prefix in Scan Code Sets 2 and 3.
FAh	Acknowledge, keyboard sends this whenever a valid command or data byte is received (except on Echo and Resend commands).
FCh	BAT Failure Code, keyboard sends this to indicate the keyboard test failed and stops scanning until a response or reset is sent.
FEh	Resend, keyboard request resend of data when data sent to it is invalid or arrives with invalid parity.
FFh	Key Detection Error or Overrun Error for Scan Code Set 2 or 3, replaces last key in the keyboard buffer if the buffer is full.
idh	Keyboard ID Response, keyboard sends a two byte ID after ACK'ing the Read ID command. The byte stream contains 83AB in LSB, MSB order. The keyboard then resumes scanning.

command F7h through FDh are NOP's on the AT and are ACK'ed but not acted upon

see 8042, MAKE CODES, BREAK CODES, INT 16,3

8042 - Speaker Controller & NMI (AT,PS/2) - Port 61h

This register can be Write and Read

bit	Description
0	PIT Channel 2 enabled (see 8253)
1	Speaker Position 1 : “out” position 0 : “in” position
2
3
4
5
6
7	Reset Keyboard status (scan code readed)

Speaker

The speaker itself has two possible positions, “in” and “out”.

This position can be set through bit 1 of port 0x61 on the Keyboard Controller.

If this bit is set (=1), the speaker will move to the “out” position, if it is cleared (=0) then the speaker will move to the “in” position.

Moving in and out repeatedly produces audible tones if the speed of repetition (the frequency) is within the range the speaker can reproduce and the human ear can hear. Also, a single movement in or out makes a click sound because it's so fast. Thus, a frequency which is too low to be heard as a tone may be heard as a rattle or buzz. (In fact, any frequency produced by this system also produces higher frequencies; look up “square wave harmonics” if you're interested.)

8042 Status Register (port 64h read)

Port	Mode	name	Description
60h	read	output register	(should only be read if Bit 0 of status port is set to 1)
60h	write	data register.	Data should only be written if Bit 1 of the status register is zero (register is empty). When this port is written Bit 3 of the status register is set to zero and the byte is treated as a data. The 8042 uses this byte if it's expecting data for a previous command, otherwise the data is written directly to the keyboard.See <A HREF=“keyboard_commands.html”>KEYBOARD COMMANDS</A> for information on programming the actual keyboard hardware.
64h	read	status register.	Can be read at any time. See table above for more information.
64h	write	command register.	Writing this port sets Bit 3 of the status register to 1 and the byte is treated as a controller command. Devices attached to the 8042 should be disabled before issuing commands that return data since data in the output register will be overwritten.

bit	Port 60h	Port 64h	8042 Status Register
0	Y	-	output register has data for system
1	Y	Y	input register has data for 8042
2	Y	Y	system flag (set to 0 after power on reset)
3	Y	Y	data in input register is command (1) or data (0)
4	Y	Y	1=keyboard enabled 0=keyboard disabled (via switch)
5	Y	Y	1=transmit timeout (data transmit not complete)
6	Y	Y	1=receive timeout (data transmit not complete)
7	Y	Y	1=even parity rec'd 0=odd parity rec'd (should be odd)

8042 Commands Related to PC Systems (Port 64h)

Command	Description
20h	Read Command Byte: current 8042 command byte is placed in port 60h.
60h	Write 8042 Command Byte: next data byte written to port 60h is placed in 8042 command register. Format (see table 1)
A4h	Password Installed Test: returned data can be read from port 60h; FA=password installed F1=no password
A5h	Load Security: bytes written to port 60h will be read until a null (0) is found.
A6h	Enable Security: works only if a password is already loaded
A7h	Disable Auxiliary Interface: sets Bit 5 of command register stopping auxiliary I/O by driving the clock line low
A8h	Enable Auxiliary Interface: clears Bit 5 of command register
A9h	Auxiliary Interface Test: clock and data lines are tested; results placed at port 60h are listed below 00 no error 01 keyboard clock line is stuck low 02 keyboard clock line is stuck high 03 keyboard data line is stuck low 04 keyboard data line is stuck high
AAh	Self Test: diagnostic result placed at port 60h, 55h=OK
ABh	Keyboard Interface Test:clock and data lines are tested; results placed at port 60h are listed above with command A9h
ACh	Diagnostic Dump: sends 16 bytes of 8042's RAM, current input port state, current output port state and 8042 program status word to port 60h in scan-code format.
ADh	Disable Keyboard Interface: sets Bit 4 of command register stopping keyboard I/O by driving the clock line low
AEh	Enable Keyboard Interface: clears Bit 4 of command register enabling keyboard interface.
C0h	Read Input Port: data is read from its input port (which is inaccessible to the data bus) and written to output register at port 60h; output register should be empty before call. (see Table 2)
C1h	Poll Input Port Low Bits: Bits 0-3 of port 1 placed in status Bits 4-7
C2h	Poll Input Port High Bits: Bits 4-7 of port 1 placed in status Bits 4-7
D0h	Read Output Port: data is read from 8042 output port (which is inaccessible to the data bus) and placed in output register; the output register should be empty. (see command D1 below)
D1h	Write Output Port: next byte written to port 60h is placed in the 8042 output port (which is inaccessible to the data bus) (see Table 3)
D2h	Write Keyboard Output Register: on PS/2 systems the next data byte written to port 60h input register is written to port 60h output register as if initiated by a device; invokes interrupt if enabled
D3h	Write Auxiliary Output Register: on PS/2 systems the next data byte written to port 60h input register is written to port 60h output register as if initiated by a device; invokes interrupt if enabled
D4h	Write Auxiliary Device: on PS/2 systems the next data byte written to input register a port at 60h is sent to the auxiliary device
E0h	Read Test Inputs: 8042 reads its T0 and T1 inputs; data is placed in output register; Bit 0 is T0, Bit 1 is T1: (See Table 4)
Fxh	Pulse Output Port: Bits 0-3 of the 8042 output port can be pulsed low for 6 æs; Bits 0-3 of command indicate which Bits should be pulsed; 0=pulse, 1=don't pulse; pulsing Bit 0 results in CPU reset since it is connected to system reset line.

Table 1

bit	8042 Command Byte
0	1=enable output register full interrupt
1	should be 0
2	1=set status register system 0=clear
3	1=override keyboard inhibit 0=allow inhibit
4	disable keyboard I/O by driving clock line low
5	disable auxiliary device, drives clock line low
6	IBM scancode translation: 0=AT 1=PC/XT
7	reserved, should be 0

Table 2

bit	8042 Input Port
0-3	undefined
4	1=enable 2nd 256K of motherboard RAM 0=disable
5	1=manufacturing jumper not installed 0=installed
6	1=primary display is MDA 0=primary display is CGA
7	1=keyboard not inhibited 0=keyboard inhibited

Table 3

bit	8042 Output Port
0	system reset line
1	gate A20
2-3	undefined
4	output buffer full
5	input buffer empty
6	keyboard clock (output)
7	keyboard data (output)

Table 4

bit	Test Input Port Bits
0	keyboard clock
1	keyboard data

PC systems previous to the AT use the 8255 PPI as a keyboard controller and use the keyboard's internal 8048.

the keyboard's internal controller buffers up to 16 bytes of make/break code information.This is common among all PC systems and shouldn't be confused with the (32 byte) keyboard buffer maintained by the BIOS.

see <A HREF=“keyboard_commands.html”>KEYBOARD COMMANDS</A> for information on programming the keyboards internal microprocessor

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