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Les deux révisions précédentesRévision précédenteProchaine révision | Révision précédente | ||
back2root:ibm-pc-ms-dos:hardware:8253 [2023/01/03 16:32] – ↷ Liens modifiés en raison d'un déplacement. frater | back2root:ibm-pc-ms-dos:hardware:8253 [2023/01/14 16:26] (Version actuelle) – frater | ||
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Ligne 26: | Ligne 26: | ||
| 41h | | 41h | ||
| 42h | | 42h | ||
- | | 43h | + | | 43h |
| 44h | | 44h | ||
| 47h | | 47h | ||
===== Port 43h ===== | ===== Port 43h ===== | ||
+ | {{anchor: | ||
+ | ^ Bit ^ 8253 Mode Control Register | ||
+ | | 0 | Counter [[# | ||
+ | | 1-3 | Counter [[# | ||
+ | | 4-5 | read/ | ||
+ | | 6-7 | counter select bits (also 8254 read back command) | ||
- | ^ Bit ^ 8253 Mode Control Register ^ | + | ==== Bits 0 - Counter |
- | | 0 | 0 : binary | + | {{anchor:cptformat}} |
- | | | + | | |
- | | | + | | |
- | | 6-7 | counter | + | |
- | + | ||
- | ==== Bits 0 - Counter mode ==== | + | |
==== Bits 1-3 - Counter Mode Bits ==== | ==== Bits 1-3 - Counter Mode Bits ==== | ||
+ | {{anchor: | ||
^ Bits ^ ^ | ^ Bits ^ ^ | ||
| 000 |mode 0, interrupt on terminal count; | | 000 |mode 0, interrupt on terminal count; | ||
Ligne 50: | Ligne 53: | ||
| 101 |mode 5, hardware triggered strobe; countdown after triggering with output high until counter zero; at zero output goes low for one CLK period| | | 101 |mode 5, hardware triggered strobe; countdown after triggering with output high until counter zero; at zero output goes low for one CLK period| | ||
- | The 1-3 bits of the control word set the operating mode of the timer. There are 6 modes in total; for modes 2 and 3, the bit 3 is ignored, so the missing modes 6 and 7 are aliases for modes 2 and 3. | + | The 1-3 bits of the control word set the operating mode of the timer. There are 6 modes in total |
+ | |||
+ | <WRAP round box> | ||
+ | For modes 2 and 3, the bit 3 is ignored, so the missing modes 6 and 7 are aliases for modes 2 and 3. | ||
+ | </ | ||
The OUT signal is linked to CPU (via Interrupt). | The OUT signal is linked to CPU (via Interrupt). | ||
Ligne 100: | Ligne 107: | ||
Suppose < | Suppose < | ||
- | {{:back2root: | + | {{back2root: |
=== Mode 4 (100): Software Triggered Strobe === | === Mode 4 (100): Software Triggered Strobe === | ||
Ligne 107: | Ligne 114: | ||
GATE low suspends the count, which resumes when GATE goes high again. | GATE low suspends the count, which resumes when GATE goes high again. | ||
- | {{:back2root: | + | {{back2root: |
=== Mode 5 (101): Hardware Triggered Strobe === | === Mode 5 (101): Hardware Triggered Strobe === | ||
Ligne 115: | Ligne 122: | ||
After receiving the Control Word and COUNT, the output will be set high. Once the device detects a rising edge on the GATE input, it will start counting. When the counter reaches 0, the output will go low for one clock cycle – after that it will become high again, to repeat the cycle on the next rising edge of GATE. | After receiving the Control Word and COUNT, the output will be set high. Once the device detects a rising edge on the GATE input, it will start counting. When the counter reaches 0, the output will go low for one clock cycle – after that it will become high again, to repeat the cycle on the next rising edge of GATE. | ||
- | {{:back2root: | + | {{back2root: |
==== Bits 4-5 - Read/ | ==== Bits 4-5 - Read/ | ||
+ | {{anchor: | ||
^ Bits ^ ^ | ^ Bits ^ ^ | ||
| 00 |latch present counter value| | | 00 |latch present counter value| | ||
Ligne 125: | Ligne 133: | ||
==== Bits 6-7 - Counter Select Bits ==== | ==== Bits 6-7 - Counter Select Bits ==== | ||
+ | {{tablelayout? | ||
+ | ^ Bits ^ ^ | ||
+ | | 00 | select counter 0 | | ||
+ | | 01 | select counter 1 | | ||
+ | | 10 | select counter 2 | | ||
+ | | 11 | read back command (8254 only, **illegal on 8253**, see [[# | ||
- | ^ Bits ^ ^ | + | ===== Read Back Command |
- | | 00 |select counter 0| | + | {{anchor: |
- | | 01 |select counter 1| | + | Read from counter register |
- | | 10 |select counter 2| | + | |
- | | 11 | read back command (8254 only, illegal on 8253, see below)| | + | |
- | + | ||
- | ===== Read Back Command | + | |
- | + | ||
- | ^ Bit ^ Read Back Command (written to Mode Control Reg) ^ | + | |
- | | | + | |
- | | | + | |
- | | | + | |
- | | | + | |
- | | | + | |
- | | | + | |
- | | 6-7 | 11 = read back command| | + | |
- | + | ||
- | + | ||
- | + | ||
- | ===== Read Back Command Status (8254 only, read from counter register) ====== | + | |
^ Bit ^ Read Back Command Status ^ | ^ Bit ^ Read Back Command Status ^ |