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back2root:ibm-pc-ms-dos:hardware:8253 [2023/01/03 16:28] – [Mode 4 (100): Software Triggered Strobe] fraterback2root:ibm-pc-ms-dos:hardware:8253 [2023/01/14 16:26] (Version actuelle) – frater
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 |  41h   |  8253   | Counter 1 RAM Refresh Counter (normally mode 2)  | |  41h   |  8253   | Counter 1 RAM Refresh Counter (normally mode 2)  |
 |  42h   |  8253   | Counter 2 Cassette and Speaker Functions         | |  42h   |  8253   | Counter 2 Cassette and Speaker Functions         |
-|  43h   |  8253   | Mode Control Register, data format (see below)   |+|  43h   |  8253   | Mode Control Register, data format (see [[#port43h|below]])   |
 |  44h   |  8254   | PS/2 extended timer                              | |  44h   |  8254   | PS/2 extended timer                              |
 |  47h   |  8254   | Channel 3 control byte                           | |  47h   |  8254   | Channel 3 control byte                           |
  
 ===== Port 43h ===== ===== Port 43h =====
 +{{anchor:port43h}}
 +^  Bit  ^ 8253 Mode Control Register                         ^
 +|  0    | Counter [[#cptformat|format]]                      |
 +|  1-3  | Counter [[#cptmode|mode]] bits                     |
 +|  4-5  | read/write/latch [[#cptlatch|format]] bits         |
 +|  6-7  | counter select bits (also 8254 read back command)  |
  
-^  Bit  ^ 8253 Mode Control Register ^ +==== Bits 0 - Counter format ==== 
-|   0   | 0 : binary Counter\\  1: decade BCD counter| +{{anchor:cptformat}} 
-|  1-3  | Counter mode bits| +|  0  |binary Counter| 
-|  4-5  | read/write/latch format bits| +|  1  |4 BCD counter|
-|  6-7  | counter select bits (also 8254 read back command)| +
- +
-==== Bits 0 - Counter mode  ====+
  
 ==== Bits 1-3 - Counter Mode Bits ==== ==== Bits 1-3 - Counter Mode Bits ====
 +{{anchor:cptmode}}
 ^  Bits  ^ ^ ^  Bits  ^ ^
 |  000  |mode 0, interrupt on terminal count;  countdown, interrupt, then wait for a new mode or count; loading a new count in the middle of a count stops the countdown| |  000  |mode 0, interrupt on terminal count;  countdown, interrupt, then wait for a new mode or count; loading a new count in the middle of a count stops the countdown|
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 |  101  |mode 5, hardware triggered strobe; countdown after triggering with output high until counter zero; at zero output goes low for one CLK period| |  101  |mode 5, hardware triggered strobe; countdown after triggering with output high until counter zero; at zero output goes low for one CLK period|
  
-The 1-3 bits of the control word set the operating mode of the timer. There are 6 modes in total; for modes 2 and 3, the bit 3 is ignored, so the missing modes 6 and 7 are aliases for modes 2 and 3.+The 1-3 bits of the control word set the operating mode of the timer. There are 6 modes in total 
 + 
 +<WRAP round box> 
 +For modes 2 and 3, the bit 3 is ignored, so the missing modes 6 and 7 are aliases for modes 2 and 3. 
 +</WRAP>
  
 The OUT signal is linked to CPU (via Interrupt). The OUT signal is linked to CPU (via Interrupt).
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 Mode 0 is used for the generation of accurate time delay under software control. In this mode, the counter will start counting from the initial COUNT value loaded into it, down to 0. Counting rate is equal to the input clock frequency. Mode 0 is used for the generation of accurate time delay under software control. In this mode, the counter will start counting from the initial COUNT value loaded into it, down to 0. Counting rate is equal to the input clock frequency.
  
-{{:back2root:ibm-pc-ms-dos:hardware:pasted:20230103-155440.png}}+{{back2root:ibm-pc-ms-dos:hardware:8253-mode0.png}}
  
 The OUT pin is set low after the Control Word is written, and counting starts one clock cycle after the COUNT is programmed. OUT remains low until the counter reaches 0, at which point OUT will be set high until the counter is reloaded or the Control Word is written. The counter wraps around to 0xFFFF internally and continues counting, but the OUT pin never changes again. The Gate signal should remain active high for normal counting. If Gate goes low, counting is suspended, and resumes when it goes high again. The OUT pin is set low after the Control Word is written, and counting starts one clock cycle after the COUNT is programmed. OUT remains low until the counter reaches 0, at which point OUT will be set high until the counter is reloaded or the Control Word is written. The counter wraps around to 0xFFFF internally and continues counting, but the OUT pin never changes again. The Gate signal should remain active high for normal counting. If Gate goes low, counting is suspended, and resumes when it goes high again.
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 After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration. After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration.
  
-{{:back2root:ibm-pc-ms-dos:hardware:pasted:20230103-160024.png}}+{{back2root:ibm-pc-ms-dos:hardware:8253-mode1.png}}
  
 The one-shot is retriggerable, hence OUT will remain low for <m>N</m> CLK pulses after any trigger. The one-shot pulse can be repeated without rewriting the same count into the counter. GATE has no effect on OUT. If a new count is written to the Counter during a oneshot pulse, the current one-shot is not affected unless the counter is retriggered. In that case, the Counter is loaded with the new count and the oneshot pulse continues until the new count expires. The one-shot is retriggerable, hence OUT will remain low for <m>N</m> CLK pulses after any trigger. The one-shot pulse can be repeated without rewriting the same count into the counter. GATE has no effect on OUT. If a new count is written to the Counter during a oneshot pulse, the current one-shot is not affected unless the counter is retriggered. In that case, the Counter is loaded with the new count and the oneshot pulse continues until the new count expires.
Ligne 89: Ligne 96:
 </WRAP> </WRAP>
  
-{{:back2root:ibm-pc-ms-dos:hardware:pasted:20230103-162148.png}}+{{back2root:ibm-pc-ms-dos:hardware:8253-mode2.png}}
  
 <WRAP round info> <WRAP round info>
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 Suppose <m>n</m> is the number loaded into the counter (the COUNT message), the output will be high for  <m>n /2</m> counts, and low for <m>n /2</m> counts. Thus, the period will be <m>n</m> counts, and if <m>n</m> is odd, the extra half-cycle is spent with OUT high. Suppose <m>n</m> is the number loaded into the counter (the COUNT message), the output will be high for  <m>n /2</m> counts, and low for <m>n /2</m> counts. Thus, the period will be <m>n</m> counts, and if <m>n</m> is odd, the extra half-cycle is spent with OUT high.
  
-{{:back2root:ibm-pc-ms-dos:hardware:pasted:20230103-162534.png}}+{{back2root:ibm-pc-ms-dos:hardware:8253-mode3.png}}
 === Mode 4 (100): Software Triggered Strobe === === Mode 4 (100): Software Triggered Strobe ===
  
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 GATE low suspends the count, which resumes when GATE goes high again. GATE low suspends the count, which resumes when GATE goes high again.
  
-{{:back2root:ibm-pc-ms-dos:hardware:pasted:20230103-162759.png}}+{{back2root:ibm-pc-ms-dos:hardware:8253-mode4.png}}
  
 === Mode 5 (101): Hardware Triggered Strobe === === Mode 5 (101): Hardware Triggered Strobe ===
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 After receiving the Control Word and COUNT, the output will be set high. Once the device detects a rising edge on the GATE input, it will start counting. When the counter reaches 0, the output will go low for one clock cycle – after that it will become high again, to repeat the cycle on the next rising edge of GATE. After receiving the Control Word and COUNT, the output will be set high. Once the device detects a rising edge on the GATE input, it will start counting. When the counter reaches 0, the output will go low for one clock cycle – after that it will become high again, to repeat the cycle on the next rising edge of GATE.
 +
 +{{back2root:ibm-pc-ms-dos:hardware:8253-mode5.png}}
 ==== Bits 4-5 - Read/Write/Latch Format Bits ==== ==== Bits 4-5 - Read/Write/Latch Format Bits ====
  
 +{{anchor:cptlatch}}
 ^  Bits  ^ ^ ^  Bits  ^ ^
 |  00  |latch present counter value| |  00  |latch present counter value|
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 ==== Bits 6-7 - Counter Select Bits ==== ==== Bits 6-7 - Counter Select Bits ====
 +{{tablelayout?rowsHeaderSource=Auto}}
 +^  Bits  ^                                                                ^
 +|  00    | select counter 0                                               |
 +|  01    | select counter 1                                               |
 +|  10    | select counter 2                                               |
 +|  11    | read back command (8254 only, **illegal on 8253**, see [[#cptread|below]])  |
  
-^  Bits  ^ ^ +===== Read Back Command Status (8254 only) ====== 
-|  00  |select counter 0| +{{anchor:cptread}} 
-|  01  |select counter 1| +Read from counter register
-|  10  |select counter 2| +
-|  11  | read back command (8254 only, illegal on 8253, see below)| +
- +
-===== Read Back Command Format  (8254 only) ===== +
- +
-^  Bit  ^ Read Back Command (written to Mode Control Reg) ^ +
-|   0   | must be zero| +
-|   1   | select counter 0| +
-|   2   | select counter 1| +
-|   3   | select counter 2| +
-|   4   | 0 = latch status of selected counters| +
-|   5   | 0 = latch count of selected counters| +
-|  6-7  | 11 = read back command| +
- +
- +
- +
-===== Read Back Command Status (8254 only, read from counter register) ======+
  
 ^  Bit  ^ Read Back Command Status ^ ^  Bit  ^ Read Back Command Status ^
back2root/ibm-pc-ms-dos/hardware/8253.1672759681.txt.gz · Dernière modification : 2023/01/03 16:28 de frater

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