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Ports | Description | |
---|---|---|
From | To | |
3B0 | 3BB | Monochrome Monitor Adapter |
3D0 | 3DC | Color Graphics Adapter (mapped similarly) |
Adapter | Mode | Description | |
---|---|---|---|
Mono | Color | ||
3B0 | 3D0 | R/W | port address decodes to 3B4/3D4 |
3B1 | 3D1 | R/W | port address decodes to 3B5/3D5 |
3B2 | 3D2 | R/W | port address decodes to 3B4/3D4 |
3B3 | 3D3 | R/W | port address decodes to 3B5/3D5 |
3B4 | 3D4 | R/W | 6845 index register, selects which register [0-11h] is to be accessed through port 3B5/3D5 |
3B5 | 3D5 | R/W | 6845 data register [0-11h] selected by port 3B4/3D4. registers 0C-0F may be read. If a read occurs without the adapter installed, FFh is returned. |
3B6 | 3D6 | R/W | port address decodes to 3B4/3D4 |
3B7 | 3D7 | R/W | port address decodes to 3B5/3D5 |
3B8 | 3D8 | R/W | 6845 mode control register |
N/A | 3D9 | R/W | color select register on color adapter |
3BA | 3DA | R | status register (read only) |
3BB | 3DB | R | light pen strobe reset |
N/A | 3DC | R | preset light pen latch |
3DE | R/W | Extended Register | |
3DF | R/W | Extended Registers Data | |
N/A | 3DF | W | CRT/CPU page register (PCjr only) |
Registers Accessed through ports 3B5 & 3D5 | VALID VALUES | ||||
---|---|---|---|---|---|
register | Descrption | MONO | CO40 | CO80 | GRPH |
00 | Horiz. total characters | 61 | 38 | 71 | 38 |
01 | Horiz. displayed characters per line | 50 | 28 | 50 | 28 |
02 | Horiz. synch position | 52 | 2D | 5A | 2D |
03 | Horiz. synch width in characters | 0F | 0A | 0A | 0A |
04 | Vert. total lines | 19 | 1F | 1F | 7F |
05 | Vert. total adjust (scan lines) | 06 | 06 | 06 | 06 |
06 | Vert. displayed rows | 19 | 19 | 19 | 64 |
07 | Vert. synch position (character rows) | 19 | 1C | 1C | 70 |
08 | Interlace mode | 02 | 02 | 02 | 02 |
09 | Maximum scan line address | 0D | 07 | 07 | 01 |
0A | Cursor start (scan line) | 0B | 06 | 06 | 06 |
0B | Cursor end (scan line) | 0C | 07 | 07 | 07 |
0C | Start address (MSB) | 00 | 00 | 00 | 00 |
0D | Start address (LSB) | 00 | 00 | 00 | 00 |
0E | Cursor address (MSB) (read/write) | 00 | – | – | – |
0F | Cursor address (LSB) (read/write) | 00 | – | – | – |
10 | Light pen (MSB) (read only) | – | – | – | – |
11 | Light pen (LSB) (read only) | – | – | – | – |
Bit | 3B8 CRT Control Port |
---|---|
0 | 1 = 80×25 text |
1-2 | unused |
3 | 1 = enable video out |
4 | unused |
5 | 0 = blink off 1 = blinking on |
6-7 | unused |
bit 0 MUST be always set to 1, if set to 0, adapter will force CPU to wait for an never set signal and hang
Bit | 3D8 CRT Control Port |
---|---|
0 | Text mode: 0 = 40×25 text 1 = 80×25 text |
1 | Video Mode: 0 = text 1 = graphics |
2 | Color mode: 0 = color 1 = B/W |
3 | 1 = enable video signal |
4 | 1 = 640×200 B/W graphics |
5 | 0 = no blink 1 = blinking on |
6-7 | unused |
Bit | 3D9 Color Select Register (3B9 not used) |
---|---|
0-2 | border color (indexed) |
3 | background intensity setting |
5-7 | unused |
Bit | 3D9 Color Select Register (3B9 not used) |
---|---|
0-2 | background color (indexed color) |
3 | enable background intensity |
4 | unused |
5 | 0 = palette 0 1 = palette 1 (see below) |
6-7 | unused |
Bit | 3DA Status Register |
---|---|
0 | retrace signal 0: no retrace signal 1: horizontal or vertical retrace |
1 | optical pen 0: pen released 1: pen pushed |
2 | optical pen 0: not present 1: present |
3 | Vertical Retrace 0: no retrace in progress 1: retrace in progress |
4-5 | diagnostics (reserved) |
6-7 | unused |
Bit | 3DE Extended Registers |
---|---|
0-4 | Extension Data Registers |
5-7 | Reserved |
Bit | 3DF CRT / Processor Page Register |
---|---|
0 | CRT Page 0 |
1 | CRT Page 1 |
2 | CRT Page 2 |
3 | Processor Page 0 |
4 | Processor Page 1 |
5 | Processor Page 3 |
6 | Video Address mode 0 |
7 | Video Address mode 1 |
These bits select which 16K byte memory-page between 00000 to hex IFFFF is being displayed. If there is no expansion RAM in the system, the high- order bit is a “I don't care” , and only 4 pages are supported. For graphics modes which require 32K bytes the low-order bit is a “I don't care”
These bits select the 16K byte memory-page region where memory cycles to B8000 are redirected. If there is no expansion RAM installed in the system, the high-order bit is a I don't care I and only 4 pages are supported.
These bits control whether the row scan addresses are used as part of the memory address. These should be programmed as follows:
Video Address Mode | ||
---|---|---|
1 (Bit 7) | 0 (Bit 6) | Resulting Modes |
0 | 0 | All Alpha Modes |
0 | 1 | Low Resolution Graphics Modes |
1 | 1 | High Resolution Graphics Modes |
1 | 0 | Unused, Reserved |