Table des matières
Instruction Timing
Instruction Clock Cycle Calculation
Some instructions require additional clock cycles due to a “Next Instruction Component” identified by a “+m” in the instruction clock cycle listings. This is due to the prefetch queue being purge on a control transfers. Below is the general rule for calculating “m”:
| 88/86 | not applicable |
| 286 | “m” is the number of bytes in the next instruction |
| 386 | “m” is the number of components in the next instruction (the instruction coding (each byte), plus the data and the displacement are all considered components) |
8088/8086 Effective Address (EA) Calculation
| Description | Clock Cycles |
|---|---|
| Displacement | 6 |
| Base or Index (BX,BP,SI,DI) | 5 |
| Displacement+(Base or Index) | 9 |
| Base+Index (BP+DI,BX+SI) | 7 |
| Base+Index (BP+SI,BX+DI) | 8 |
| Base+Index+Displacement (BP+DI,BX+SI) | 11 |
| Base+Index+Displacement (BP+SI+disp,BX+DI+disp) | 12 |
- add 4 cycles for word operands at odd addresses
- add 2 cycles for segment override
- 80188/80186 timings differ from those of the 8088/8086/80286
Task State Calculation
“TS” is defined as switching from VM/486 or 80286 TSS to one of the following:
| New Task | |||||
|---|---|---|---|---|---|
| Old Task | 486 TSS (VM=0) | 486 TSS (VM=1) | 386 TSS (VM=0) | 386 TSS (VM=1) | 286 TSS |
| 386 TSS (VM=0) | 309 | 226 | 282 | ||
| 386 TSS (VM=1) | 314 | 231 | 287 | ||
| 386 CPU/286 TSS | 307 | 224 | 280 | ||
| 486 CPU/286 TSS | 199 | 177 | 180 | ||
Miscellaneous
- all timings are for best case and do not take into account wait states, instruction alignment, the state of the prefetch queue, DMA refresh cycles, cache hits/misses or exception processing. - to convert clocks to nanoseconds divide one microsecond by the processor speed in MegaHertz: