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+ | ~~TOC 2-5~~ | ||
+ | ====== PORTS Common I/O Port Addresses ====== | ||
+ | |||
+ | <WRAP round important> | ||
+ | Port addresses are not always constant across PC, AT and PS/2 | ||
+ | |||
+ | Unless marked, port addresses are relative to PC and XT only | ||
+ | </ | ||
+ | |||
+ | ===== Quick Jump ===== | ||
+ | <nspages -h1 -simpleList -subns -exclude: | ||
+ | |||
+ | [[back2root: | ||
+ | |||
+ | ===== 000h-00Fh - 8237 DMA controller ===== | ||
+ | |||
+ | | 000h | Channel 0 address register | ||
+ | | 001h | Channel 0 word count | | ||
+ | | 002h | Channel 1 address register | ||
+ | | 003h | Channel 1 word count | | ||
+ | | 004h | Channel 2 address register | ||
+ | | 005h | Channel 2 word count | | ||
+ | | 006h | Channel 3 address register | ||
+ | | 007h | Channel 3 word count | | ||
+ | | 008h | Status/ | ||
+ | | 009h | Request register | ||
+ | | 00Ah | Mask register | ||
+ | | 00Bh | Mode register | ||
+ | | 00Ch | Clear MSB/LSB flip flop | | ||
+ | | 00Dh | Master clear temp register | ||
+ | | 00Eh | Clear mask register | ||
+ | | 00Fh | Multiple mask register | ||
+ | |||
+ | ===== 010h-01Fh - 8237 DMA Controller (PS/2 model 60 & 80), reserved (AT) ===== | ||
+ | |||
+ | ===== 020h-02Fh - 8259A Master Programmable Interrupt Controller ===== | ||
+ | {{tablelayout? | ||
+ | | 020h | [[back2root: | ||
+ | | 021h | [[back2root: | ||
+ | |||
+ | ===== 030-03F | ||
+ | |||
+ | ===== 040-05F - 8253 or 8254 Programmable Interval Timer (PIT) ===== | ||
+ | |||
+ | | 040h | [[back2root: | ||
+ | | 041h | [[back2root: | ||
+ | | 042h | [[back2root: | ||
+ | | 043h | [[back2root: | ||
+ | | 044h | [[back2root: | ||
+ | | 047h | [[back2root: | ||
+ | |||
+ | ===== 060h-067h - 8255 Programmable Peripheral Interface - PPI (PC,XT, PCjr) ===== | ||
+ | |||
+ | | 060h | [[back2root: | ||
+ | | 061h | [[back2root: | ||
+ | | 062h | [[back2root: | ||
+ | | 063h | [[back2root: | ||
+ | |||
+ | ===== 060h-06Fh - 8042 Keyboard Controller | ||
+ | {{tablelayout? | ||
+ | | 060h | [[back2root: | ||
+ | | 061h | [[back2root: | ||
+ | | 064h | [[back2root: | ||
+ | |||
+ | ===== 070h-07Fh - CMOS RAM ===== | ||
+ | |||
+ | | 070h | CMOS RAM/RTC, also NMI enable/ | ||
+ | | 071h | CMOS RAM data (AT, | ||
+ | |||
+ | ===== 080h-090h - DMA Page Registers ===== | ||
+ | | 080h | Manufacturer systems checkpoint port (used during POST) | | ||
+ | | 081h | High order 4 bits of DMA channel 2 address | ||
+ | | 082h | High order 4 bits of DMA channel 3 address | ||
+ | | 083h | High order 4 bits of DMA channel 1 address | ||
+ | |||
+ | ===== 090h-097h - POS/ | ||
+ | | 090h | Central arbitration control Port | | ||
+ | | 091h | Card selection feedback | ||
+ | | 092h | System control and status register | ||
+ | | 094h | System board enable/ | ||
+ | | 095h | Reserved | ||
+ | | 096h | Adapter enable/ | ||
+ | | 097h | Reserved | ||
+ | |||
+ | ===== 0A0h-0BFh - Second 8259 Programmable Interrupt Controller (AT, PS/2) ===== | ||
+ | {{tablelayout? | ||
+ | | 0A0h | | NMI Mask Register (PC,XT) (write 80h to enable NMI, 00h disable) | ||
+ | | 0A0h | [[back2root: | ||
+ | | 0A1h | [[back2root: | ||
+ | |||
+ | |||
+ | ===== 0C0h-0DFh - 8237 DMA controller 2 (AT) ===== | ||
+ | | 0C0h | TI SN76496 Programmable Tone/Noise Generator (PCjr) | ||
+ | | 0C2h | DMA channel 3 selector | ||
+ | |||
+ | ===== 0E0h-0EFh - Reserved ===== | ||
+ | |||
+ | ===== 0F0h-0FFh - Math coprocessor (AT, PS/2) ===== | ||
+ | |||
+ | ===== 0F0h-0F5h - PCjr Disk Controller ===== | ||
+ | | 0F0h | Disk Controller | ||
+ | | 0F2h | Disk Controller control port | | ||
+ | | 0F4h | Disk Controller status register | ||
+ | | 0F5h | Disk Controller data port | | ||
+ | |||
+ | ===== 0F8h-0FFh - Reserved for future microprocessor extensions ===== | ||
+ | |||
+ | ===== 100h-10Fh - POS Programmable Option Select (PS/2) ===== | ||
+ | | 100h | POS Register 0, Adapter ID byte (LSB) | | ||
+ | | 101h | POS Register 1, Adapter ID byte (MSB) | | ||
+ | | 102h | POS Register 2, Option select data byte 1\\ * Bit 0 is card enable (CDEN) | ||
+ | | 103h | POS Register 3, Option select data byte 2 | | ||
+ | | 104h | POS Register 4, Option select data byte 3 | | ||
+ | | 105h | POS Register 5, Option select data byte 4\\ * Bit 7 is (-CHCK)\\ | ||
+ | | 106h | POS Register 6, subaddress extension (LSB) | | ||
+ | | 107h | POS Register 7, subaddress extension (MSB) | | ||
+ | |||
+ | ===== 110h-1EFh - System I/O channel ===== | ||
+ | |||
+ | ===== 170h-17Fh - Fixed disk 1 (AT) ===== | ||
+ | | 170h | disk 1 data | | ||
+ | | 171h | disk 1 error | | ||
+ | | 172h | disk 1 sector count | | ||
+ | | 173h | disk 1 sector number | ||
+ | | 174h | disk 1 cylinder low | | ||
+ | | 175h | disk 1 cylinder high | | ||
+ | | 176h | disk 1 drive/ | ||
+ | | 177h | disk 1 status | ||
+ | |||
+ | ===== 1F0-1FF | ||
+ | | 1F0h | disk 0 data | | ||
+ | | 1F1h | disk 0 error | | ||
+ | | 1F2h | disk 0 sector count | | ||
+ | | 1F3h | disk 0 sector number | ||
+ | | 1F4h | disk 0 cylinder low | | ||
+ | | 1F5h | disk 0 cylinder high | | ||
+ | | 1F6h | disk 0 drive/ | ||
+ | | 1F7h | disk 0 status | ||
+ | |||
+ | ===== 200h-20Fh - Game Adapter (see GAME PORT or ~JOYSTICK~) ===== | ||
+ | |||
+ | ===== 210h-217h | ||
+ | {{tablelayout? | ||
+ | | 210h | ||
+ | | 211h | ||
+ | | 212h | ||
+ | | 213h | ||
+ | | 214h-215h | ||
+ | | 214h | ||
+ | | 214h | ||
+ | | 215h | ||
+ | | : | | ||
+ | | 21Fh | ||
+ | |||
+ | ===== 220-26F | ||
+ | |||
+ | ===== 270-27F | ||
+ | | 278h | data port | | ||
+ | | 279h | status port | | ||
+ | | 27Ah | control port | | ||
+ | |||
+ | ===== 280h-2AFh - Reserved for I/O channel ===== | ||
+ | |||
+ | ===== 2A2h-2A3h - MSM58321RS clock ===== | ||
+ | |||
+ | ===== 2B0h-2DFh - Alternate EGA, or 3270 PC video (XT, AT) ===== | ||
+ | |||
+ | | 2E0h | Alternate EGA/ | ||
+ | | 2E1h | GPIB Adapter (AT) | | ||
+ | |||
+ | ===== 2E2h-2E3h - Data acquisition adapter (AT) ===== | ||
+ | |||
+ | ===== 2E8h-2EFh - COM4 non PS/2 UART (Reserved by IBM) ===== | ||
+ | |||
+ | see [[# | ||
+ | |||
+ | |||
+ | |||
+ | ===== 2F0h-2F7h - Reserved ===== | ||
+ | |||
+ | ===== 2F8h-2FFh - COM2 Second Asynchronous Adapter ===== | ||
+ | |||
+ | Primary Asynchronous Adapter for PCjr | ||
+ | |||
+ | See [[# | ||
+ | ===== 300h-31Fh - Prototype Experimentation Card (except PCjr) ===== | ||
+ | Periscope hardware debugger | ||
+ | |||
+ | ===== 320h-32Fh - Hard Disk Controller | ||
+ | | 320h | | Read from/Write to controller | ||
+ | | 321h | Read | Controller Status | ||
+ | | | ||
+ | | 322h | Write | generate controller select pulse | | ||
+ | | 323h | Write | Pattern to DMA and interrupt mask register (see ports 0F, | ||
+ | | 324h | | disk attention/ | ||
+ | |||
+ | ===== 330h-33Fh - Reserved for XT/370 ===== | ||
+ | |||
+ | ===== 340h-35Fh - Reserved for I/O channel ===== | ||
+ | |||
+ | ===== 360h-36Fh - PC Network ===== | ||
+ | |||
+ | ===== 370h-377h - Floppy disk controller (except PCjr) ===== | ||
+ | | 372h | Diskette digital output | ||
+ | | 374h | Diskette controller status | ||
+ | | 375h | Diskette controller data | | ||
+ | | 376h | Diskette controller data | | ||
+ | | 377h | Diskette digital input | | ||
+ | |||
+ | ===== 378h-37Fh - Second Parallel Printer (see ~PARALLEL PORT~) ===== | ||
+ | First Parallel Printer (see PARALLEL PORT) | ||
+ | |||
+ | | 378h | data port | | ||
+ | | 379h | status port | | ||
+ | | 37Ah | control port | | ||
+ | |||
+ | ===== 380h-38Fh - Secondary Binary Synchronous Data Link Control (SDLC) adapter ===== | ||
+ | | 380h | On board [[back2root: | ||
+ | | 381h | On board [[back2root: | ||
+ | | 382h | On board [[back2root: | ||
+ | | 383h | On board [[back2root: | ||
+ | | 384h | On board [[back2root: | ||
+ | | 385h | On board [[back2root: | ||
+ | | 386h | On board [[back2root: | ||
+ | | 387h | On board [[back2root: | ||
+ | |||
+ | |||
+ | | 388h | On board 8273 | read: status\\ Write: Command | ||
+ | | 389h | On board 8273 | write: parameter\\ read: response | ||
+ | | 38Ah | On board 8273 | transmit interrupt status | ||
+ | | 38Bh | On board 8273 | receiver interrupt status | ||
+ | | 38Ch | On board 8273 | data | | ||
+ | |||
+ | ===== 390h-39Fh - Cluster Adapter ===== | ||
+ | |||
+ | ===== 3A0h-3AFh - Primary Binary Synchronous Data Link Control (SDLC) adapter ===== | ||
+ | {{tablelayout? | ||
+ | | 3A0h | On board [[back2root: | ||
+ | | 3A1h | On board [[back2root: | ||
+ | | 3A2h | On board [[back2root: | ||
+ | | 3A3h | On board [[back2root: | ||
+ | | 3A4h | On board [[back2root: | ||
+ | | 3A5h | On board [[back2root: | ||
+ | | 3A6h | On board [[back2root: | ||
+ | | 3A7h | On board [[back2root: | ||
+ | |||
+ | | 3A8h | On board 8251 | data | | ||
+ | | 3A9h | On board 8251 | command/ | ||
+ | |||
+ | ===== 3B0h-3BFh - Monochrome Display Adapter (write only) ===== | ||
+ | {{tablelayout? | ||
+ | | 3B0h | | port address decodes to 3B4 | | ||
+ | | 3B1h | | port address decodes to 3B5 | | ||
+ | | 3B2h | | port address decodes to 3B4 | | ||
+ | | 3B3h | | port address decodes to 3B5 | | ||
+ | | 3B4h | [[back2root: | ||
+ | | 3B5h | [[back2root: | ||
+ | | 3B6h | | port address decodes to 3B4 | | ||
+ | | 3B7h | | port address decodes to 3B5 | | ||
+ | | 3B8h | [[back2root: | ||
+ | | 3B9h | | reserved for color select register on color adapter | ||
+ | | 3BAh | | status register (read only) | | ||
+ | | 3BBh | | reserved for light pen strobe reset | | ||
+ | |||
+ | ===== 3BCh-3BFh - Primary Parallel Printer Adapter (see ~PARALLEL PORT~) ===== | ||
+ | | 3BCh | parallel 1, data port | | ||
+ | | 3BDh | parallel 1, status port | | ||
+ | | 3BEh | parallel 1, control port | | ||
+ | |||
+ | ===== 3C0h-3CFh - EGA/VGA ===== | ||
+ | | 3C0h | VGA attribute and sequencer register | ||
+ | | 3C1h | Other video attributes | ||
+ | | 3C2h | EGA, VGA, CGA input status 0 | | ||
+ | | 3C3h | Video subsystem enable | ||
+ | | 3C4h | CGA, EGA, VGA sequencer index | | ||
+ | | 3C5h | CGA, EGA, VGA sequencer | ||
+ | | 3C6h | VGA video DAC PEL mask | | ||
+ | | 3C7h | VGA video DAC state | | ||
+ | | 3C8h | VGA video DAC PEL address | ||
+ | | 3C9h | VGA video DAC | | ||
+ | | 3CAh | VGA graphics 2 position | ||
+ | | 3CCh | VGA graphics 1 position | ||
+ | | 3CDh | VGA feature control | ||
+ | | 3CEh | VGA graphics index | | ||
+ | | 3CFh | Other VGA graphics | ||
+ | |||
+ | see [[ega-vga-registers|EGA/ | ||
+ | |||
+ | ===== 3D0h-3DFh - Color Graphics Monitor Adapter ===== | ||
+ | |||
+ | <WRAP round info > | ||
+ | ports 3D0h-3DBh are write only, see [[back2root: | ||
+ | </ | ||
+ | |||
+ | | 3D0h | [[back2root: | ||
+ | | 3D1h | [[back2root: | ||
+ | | 3D2h | [[back2root: | ||
+ | | 3D3h | [[back2root: | ||
+ | | 3D4h | [[back2root: | ||
+ | | 3D5h | [[back2root: | ||
+ | | 3D6h | [[back2root: | ||
+ | | 3D7h | [[back2root: | ||
+ | | 3D8h | [[back2root: | ||
+ | | 3D9h | [[back2root: | ||
+ | | 3DAh | [[back2root: | ||
+ | | 3DBh | [[back2root: | ||
+ | | 3DCh | [[back2root: | ||
+ | | 3DFh | [[back2root: | ||
+ | |||
+ | ===== 3E8h-3EFh - COM3 non PS/2 UART (Reserved by IBM) ===== | ||
+ | |||
+ | (see [[# | ||
+ | ===== 3F0h-3F7h - Floppy disk controller (except PCjr) ===== | ||
+ | {{tablelayout? | ||
+ | | 3F0h | Diskette controller status A | | ||
+ | | 3F1h | Diskette controller status B | | ||
+ | | 3F2h | controller control port | | ||
+ | | 3F4h | controller status register | ||
+ | | 3F5h | data register (write 1-9 byte command, see [[back2root: | ||
+ | | 3F6h | Diskette controller data | | ||
+ | | 3F7h | Diskette digital input | | ||
+ | |||
+ | ===== 3F8h-3FFh - COM1 Primary Asynchronous Adapter ===== | ||
+ | {{anchor: | ||
+ | {{tablelayout? | ||
+ | | 3220h-3227h | ||
+ | | 3228h-322Fh | ||
+ | | 4220h-4227h | ||
+ | | 4228h-422Fh | ||
+ | | 5220h-5227h | ||
+ | | 5228h-522Fh |