read data (toggles w/positive transition in -RD DATA)
4
write data (toggles w/positive transition in WR DATA)
5
drive select
6-7
reserved
FDC Digital Output Register at 3F2h (all systems)
bit
port 3F2h (write only)
0-1
floppy drive select (0=A, 1=B, 2=floppy C, …)
2
1 = FDC enable, 0 = hold FDC at reset
3
1 = DMA & I/O interface enabled (reserved PS/2)
4
1 = turn floppy drive A motor on
5
1 = turn floppy drive B motor on
6
1 = turn floppy drive C motor on; (reserved PS/2)
7
1 = turn floppy drive D motor on; (reserved PS/2)
used to control drive motors, drive selection, and feature enable
PS/2 only uses bit 0 for floppy drive select; bit 1 is reserved
PS/2 only uses bits 5 & 4 for motor enable; bits 7&6 are reserved
all DOR bits are cleared during controller reset
FDC Main Status Register at 3F4h (all systems)
bit
port 3F4h (read only)
0
floppy drive 0 in seek mode/busy
1
floppy drive 1 in seek mode/busy
2
floppy drive 2 in seek mode/busy (reserved PS/2)
3
floppy drive 3 in seek mode/busy (reserved PS/2)
4
FDC read or write command in progress
5
FDC is in non-DMA mode
6
I/O direction; 1 = FDC to CPU; 0 = CPU to FDC
7
data reg ready for I/O to/from CPU (request for master)
FDC Command Status Register 0 at 3F5h (all systems)
bit
Command Status Register 0 at port 3F5h
0-1
unit selected at interrupt (0=A, 1=B, 2=…)
2
head number at interrupt (head 0 or 1)
3
not ready on read/write or SS access to head 1
4
equipment check (see note)
5
set to 1 when FDD completes a seek command
6-7
last command status (see below)
Bits 7-6
Last Command Status
00
command terminated successfully
01
command execution started but terminated abnormally
10
invalid command issued
11
command terminated abnormally due to a change in state of the Ready Signal from the FDC (reserved on PS/2)
equipment check can occur if FDD signals a fault or track zero is not found after 77 steps on a recalibrate command
PS/2 only uses bits 1-0 for drive (values are 01b and 10b)
FDC Command Status Register 1 at 3F5h (all systems)
bit
Command Status Register 1 at port 3F5h
0
FDC cannot find ID address mark (see reg 2)
1
write protect detected during write
2
FDC cannot find sector ID
3
unused (always zero)
4
over-run; FDC not serviced in reasonable time
5
data error (CRC) in ID field or data field
6
unused (always zero)
7
end of cylinder; sector# greater than sectors/track
bit 0 of Status Register 1 and bit 4 of Status Register 2 are related and mimic each other
3F5h - FDC Command Status Register 2 (all systems)
bit
Command Status Register 2 at port 3F5h
0
missing address mark in data field
1
bad cylinder, ID not found and Cyl Id=FFh
2
scan command failed, sector not found in cylinder
3
scan command equal condition satisfied
4
wrong cylinder detected
5
CRC error detected in sector data
6
sector with deleted data address mark detected
7
unused (always zero)
bit 0 of Status Register 1 and bit 4 of Status Register 2 are related and mimic each other
3F5h - FDC Command Status Register 3 (FDD status, all systems)
bit
Floppy Disk Drive Status at port 3F5h
0-1
FDD unit selected status (0=A, 1=B, 2=…)
2
FDD side head select status (0=head 0, 1=head 1)
3
FDD two sided status signal
4
FDD track zero status signal
5
FDD ready status signal
6
FDD write protect status signal
7
FDD fault status signal
3F7h - FDC Digital Input Register (PS/2)
bit
3F7h PS/2 Digital Input Register (read only)
0
high density select
1-6
reserved
7
diskette change
3F7h - FDC Configuration Control Register (PS/2)
bit
3F7h PS/2 Config. Control Register (write only)
0-1
DRC1, DRC0 (see below)
2-7
reserved
DRC1
DRC0
0
0
500000 bit per second mode
0
1
reserved
1
0
250000 bit per second mode
1
1
reserved
Digital Input Register is used to sense the state of the (-diskette change) and the (-high density select) signals
Configuration Control Register is used to set the transfer rate
FDC Programming Considerations
Three phases of command execution:
Command phase; commands are sent from the CPU to the FDC via port 3F5h; bit 6 of the Status Register at 3F4h must be zero
Execution phase; FDC executes instruction & generates INT 6
Result phase; status and other information is available to CPU; INT 6 sets bit 7 of BIOS Data Area location 40:3E which can be polled for completion status
Example of a read operation:
turn disk motor on and set delay time for drive spin up
perform seek operation; wait for disk interrupt
prepare DMA chip to move data to memory
send read command and wait for transfer complete interrupt
PS/2 systems use the 8272A diskette controller which is software and port compatible with the NEC µPD765
accessed through ports 3F0h-3F7h; NEC µPD765 is accessed through ports 3F2h, 3F4h and 3F5h; the 8272A uses ports 3F0h, 3F1h, 3F2h, 3F4h, 3F5h and 3F7h
data, command and status registers are all accessed through port 3F5h a register stack with one address presented to the bus
bit 7 of BIOS Data Area byte 40:3E can be polled to determine if a disk operation has completed; this bit is set by the interrupt handler when the operation has completed; it should be reset before continuing on with the next FDC operation
