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Les deux révisions précédentesRévision précédenteProchaine révision | Révision précédente | ||
back2root:ibm-pc-ms-dos:hardware:8272-pd765 [2023/02/23 22:23] – [Tableau] frater | back2root:ibm-pc-ms-dos:hardware:8272-pd765 [2023/02/23 22:30] (Version actuelle) – [Key to Abbreviations] frater | ||
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|Invalid Command | |Invalid Command | ||
|result byte 0: | |result byte 0: | ||
+ | |||
+ | === Key to Abbreviations === | ||
+ | {{tablelayout? | ||
+ | ^ HD | Head Number Selected | ||
+ | ^ MT | Multi-Track | ||
+ | ^ MF | MFM mode | | ||
+ | ^ ND | Non-DMA mode | | ||
+ | ^ SK | SKip Deleted-data address mark | | ||
+ | ^ US0 | drive select bit 0 | | ||
+ | ^ US1 | drive select bit 1 | | ||
+ | |||
+ | * Head Load Time = 2 to 254ms in 2ms increments | ||
+ | * Head Unload Time = 16 to 240ms in 16ms increments | ||
+ | * Step Rate Time = 1 to 16ms in 1ms increments | ||
+ | |||
<WRAP round box> | <WRAP round box> | ||
* PS/2 systems use the 8272A diskette controller which is software and port compatible with the NEC µPD765 | * PS/2 systems use the 8272A diskette controller which is software and port compatible with the NEC µPD765 | ||
- | * accessed through ports 3F0h-3F7h; NEC µPD765 is accessed through ports 3F2h, 3F4h and 3F5h; the 8272A uses ports 3F0h, 3F1h, 3F2h, 3F4h, 3F5h and 3F7h | + | * accessed through ports 3F0h-3F7h;\\ NEC µPD765 is accessed through ports 3F2h, 3F4h and 3F5h;\\ the 8272A uses ports 3F0h, 3F1h, 3F2h, 3F4h, 3F5h and 3F7h |
* data, command and status registers are all accessed through port 3F5h a register stack with one address presented to the bus | * data, command and status registers are all accessed through port 3F5h a register stack with one address presented to the bus | ||
* bit 7 of BIOS Data Area byte 40:3E can be polled to determine if a disk operation has completed; this bit is set by the interrupt handler when the operation has completed; it should be reset before continuing on with the next FDC operation | * bit 7 of BIOS Data Area byte 40:3E can be polled to determine if a disk operation has completed; this bit is set by the interrupt handler when the operation has completed; it should be reset before continuing on with the next FDC operation | ||
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* see [[back2root: | * see [[back2root: | ||
- | * see [[back2root: | + | * see [[back2root: |