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Les deux révisions précédentesRévision précédenteProchaine révision | Révision précédente | ||
back2root:ibm-pc-ms-dos:hardware:8259 [2022/12/29 13:03] – [Initialization Command Word 1 at Port 20h and A0h] frater | back2root:ibm-pc-ms-dos:hardware:8259 [2023/01/16 16:33] (Version actuelle) – [8259 Programmable Interrupt Controller Notes] frater | ||
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Ligne 4: | Ligne 4: | ||
==== Initialization Command Word 1 at Port 20h and A0h ==== | ==== Initialization Command Word 1 at Port 20h and A0h ==== | ||
- | ^ Bit ^ Initiali | + | ^ Bit ^ Initialization Command Word 1 |
- | | 0 | 0=no ICW4 needed\\ | + | | 0 | 1=ICW4 is needed\\ |
- | | 1 | 0=cascading | + | | 1 | 1=single |
- | | 2 | 0=8 byte int vectors\\ 1=4 byte interrupt | + | | 2 | 1=4 byte interrupt vector\\ 0=8 byte int vectors |
- | | 3 | 0=edge triggered mode\\ | + | | 3 | 1=level triggered mode\\ |
| 4 | must be 1 for ICW1 (port must also be 20h or A0h) | | | 4 | must be 1 for ICW1 (port must also be 20h or A0h) | | ||
| 5-7 | must be zero for PC systems | | 5-7 | must be zero for PC systems | ||
+ | |||
==== Initialization Command Word 2 at Port 21h and A1h ==== | ==== Initialization Command Word 2 at Port 21h and A1h ==== | ||
- | < | + | ^ Bit ^ Initialization Command Word 2 ^ |
- | |7|6|5|4|3|2|1|0| ICW2 | + | | 0-2 | 000= on 80x86 systems| |
- | | | | | | `-------- | + | | 3-7 | A7-A3 of 80x86 interrupt vector| |
- | `----------------- A7-A3 of 80x86 interrupt vector | + | |
- | </ | + | |
==== Initialization Command Word 3 at Port 21h and A1h ==== | ==== Initialization Command Word 3 at Port 21h and A1h ==== | ||
- | < | + | ^ bit ^ Initialization Command Word 3 for Master Device^ |
- | |7|6|5|4|3|2|1|0| | + | | 0 |1=interrupt request 0 has slave\\ 0=no slave| |
- | | | | | | | | `---- 1=interrupt request 0 has slave, 0=no slave | + | | 1 |1=interrupt request 1 has slave\\ 0=no slave| |
- | | | | | | | `----- | + | | 2 |1=interrupt request 2 has slave\\ 0=no slave| |
- | | | | | | `------ | + | | 3 |1=interrupt request 3 has slave\\ 0=no slave| |
- | | | | | `------- | + | | 4 |1=interrupt request 4 has slave\\ 0=no slave| |
- | | | | `-------- | + | | 5 |1=interrupt request 5 has slave\\ 0=no slave| |
- | | | `--------- | + | | 6 |1=interrupt request 6 has slave\\ 0=no slave| |
- | | + | | |
- | `----------- | + | |
- | </ | + | |
- | < | + | |
- | |7|6|5|4|3|2|1|0| | + | |
- | | | | | | `-------- master interrupt request slave is attached to | + | |
- | | + | |
- | </ | + | |
- | ==== Initialization Command Word 4 at Port 21h and A1h ==== | + | |
- | < | + | |
- | |7|6|5|4|3|2|1|0| | + | |
- | | | | | | | | `---- 1 for 80x86 mode, 0 = MCS 80/85 mode | + | |
- | | | | | | | `----- 1 = auto EOI, 0=normal EOI | + | |
- | | | | | `-------- slave/ | + | |
- | | | | `--------- 1 = special fully nested mode (SFNM), 0=sequential | + | |
- | | + | |
- | </ | + | |
+ | ^ bit ^ Initialization Command Word 3 for Master Device^ | ||
+ | | 0-2 | master interrupt request slave is attached to | | ||
+ | | 3-7 | must be zero| | ||
+ | ==== Initialization Command Word 4 at Port 21h and A1h ==== | ||
+ | ^ Bit ^ Initialization Command Word 4 ^ | ||
+ | | | ||
+ | | | ||
+ | | 2-3 | slave/ | ||
+ | | | ||
+ | | 5-7 | unused (set to zero)| | ||
^ Bits |^ Buffering Mode ^ | ^ Bits |^ Buffering Mode ^ | ||
Ligne 56: | Ligne 50: | ||
==== Operation Control Word 1 / Interrupt Mask Reg. (Ports 21h & A1h) ==== | ==== Operation Control Word 1 / Interrupt Mask Reg. (Ports 21h & A1h) ==== | ||
- | < | + | |
- | |7|6|5|4|3|2|1|0| OCW1 - IMR Interrupt Mask Register | + | ^ bit ^ Operation Control Word 1 - IMR Interrupt Mask Register^ |
- | | | | | | | | `---- 0 = service IRQ0, 1 = mask off | + | | 0 | 0 = service IRQ0\\ 1 = mask off| |
- | | | | | | | `----- | + | | 1 | 0 = service IRQ1\\ 1 = mask off| |
- | | | | | | `------ | + | | 2 | 0 = service IRQ2\\ 1 = mask off| |
- | | | | | `------- | + | | 3 | 0 = service IRQ3\\ 1 = mask off| |
- | | | | `-------- | + | | 4 | 0 = service IRQ4\\ 1 = mask off| |
- | | | `--------- | + | | 5 | 0 = service IRQ5\\ 1 = mask off| |
- | | + | | 6 |
- | `----------- | + | | |
- | </ | + | |
==== Operation Control Word 2 / Interrupt Command Reg. (Ports 20h & A0h) ==== | ==== Operation Control Word 2 / Interrupt Command Reg. (Ports 20h & A0h) ==== | ||
- | < | + | |
- | |7|6|5|4|3|2|1|0| OCW2 - ICR Interrupt Command Register | + | ^ bit ^ Operation Control Word 2 - ICR Interrupt Command Register^ |
- | | | | | | `-------- | + | | |
- | | | | | `--------- | + | | 3 | must be 0 for OCW2| |
- | | | | `---------- | + | | 4 | must be 0 for OCW2| |
- | `--------------- EOI type (see table) | + | | 5-7 | EOI type (see table)| |
- | </ | + | |
^ Bits ||^ EOI - End Of Interrupt code (PC specific) | ^ Bits ||^ EOI - End Of Interrupt code (PC specific) | ||
Ligne 87: | Ligne 80: | ||
| 1 | | 1 | ||
- | ==== Operation Control Word 3 | + | ==== Operation Control Word 3 (Ports 20h & A0h) ==== |
- | < | + | ^ bit ^ Operation Control Word 3 ^ |
- | |7|6|5|4|3|2|1|0| OCW3 | + | | |
- | | | | | | | | `--- 1=read IRR on next read, 0=read ISR on next read | + | | 1 |
- | | | | | | | `---- 1=act on value of bit 0, 0=no action if bit 0 set | + | | 2 |
- | | | | | | `----- | + | | 3 |
- | | | | | `------ | + | | 4 |
- | | | | `------- | + | | 5 |
- | | | `-------- | + | | 6 | 1=act on value of bit 5\\ 0=no action if bit 5 set| |
- | | + | | |
- | `---------- | + | |
- | </ | + | |
==== Other Registers ==== | ==== Other Registers ==== | ||
Ligne 104: | Ligne 96: | ||
* ISR - In Service Register, tracks IRQ line currently being serviced. \\ Updated by EOI command. | * ISR - In Service Register, tracks IRQ line currently being serviced. \\ Updated by EOI command. | ||
- | ====== Hardware Interrupt Sequence of Events: ====== | + | ====== Hardware Interrupt Sequence of Events ====== |
- 8259 <A HREF=" | - 8259 <A HREF=" | ||
Ligne 118: | Ligne 110: | ||
==== Initialization ==== | ==== Initialization ==== | ||
+ | |||
- write ICW1 to port 20h | - write ICW1 to port 20h | ||
- write ICW2 to port 21h | - write ICW2 to port 21h | ||
Ligne 137: | Ligne 130: | ||
<WRAP rounded box> | <WRAP rounded box> | ||
- | see [[back2root: | + | see [[back2root: |
</ | </ |