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back2root:ibm-pc-ms-dos:hardware:8259 [2022/12/29 02:56] – [Tableau] fraterback2root:ibm-pc-ms-dos:hardware:8259 [2023/01/16 16:33] (Version actuelle) – [8259 Programmable Interrupt Controller Notes] frater
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 +~~TOC 1-4 ~~
 +
 ====== 8259 - Programmable Interrupt Controller (PIC) ====== ====== 8259 - Programmable Interrupt Controller (PIC) ======
  
 ==== Initialization Command Word 1 at Port 20h and A0h ==== ==== Initialization Command Word 1 at Port 20h and A0h ====
-<code> +^  Bit  ^ Initialization Command Word 1                      ^ 
-|7|6|5|4|3|2|1|0|  ICW1 +|  0    | 1=ICW4 is needed\\  0=no ICW4 needed               | 
- | | | | | | | `---- 1=ICW4 is needed, 0=no ICW4 needed +|  1    | 1=single 8259\\ 0=cascading 8259's                 | 
- | | | | | | `----- 1=single 8259, 0=cascading 8259's +|  2    | 1=4 byte interrupt vector\\ 0=8 byte int vectors   | 
- | | | | | `------ 1=4 byte interrupt vectors, 0=8 byte int vectors +|  3    | 1=level triggered mode\\ 0=edge triggered mode     | 
- | | | | `------- 1=level triggered mode, 0=edge triggered mode +|  4    | must be 1 for ICW1 (port must also be 20h or A0h)  | 
- | | | `-------- must be 1 for ICW1 (port must also be 20h or A0h) +|  5-7  | must be zero for PC systems                        |
- `------------- must be zero for PC systems +
-</code>+
  
 ==== Initialization Command Word 2 at Port 21h and A1h ==== ==== Initialization Command Word 2 at Port 21h and A1h ====
  
-<code> +^  Bit  ^ Initialization Command Word 2                      ^ 
-|7|6|5|4|3|2|1|0|  ICW2 +|  0-2  | 000= on 80x86 systems| 
- | | | | | `-------- 000= on 80x86 systems +|  3-7  | A7-A3 of 80x86 interrupt vector| 
- `----------------- A7-A3 of 80x86 interrupt vector +
-</code>+
  
 ==== Initialization Command Word 3 at Port 21h and A1h ==== ==== Initialization Command Word 3 at Port 21h and A1h ====
-<code> +^  bit  ^ Initialization Command Word 3 for Master Device^ 
-|7|6|5|4|3|2|1|0|  ICW3 for Master Device +|   0   |1=interrupt request 0 has slave\\ 0=no slave| 
- | | | | | | | `---- 1=interrupt request 0 has slave, 0=no slave +|   1   |1=interrupt request 1 has slave\\ 0=no slave| 
- | | | | | | `----- 1=interrupt request 1 has slave, 0=no slave +|   2   |1=interrupt request 2 has slave\\ 0=no slave| 
- | | | | | `------ 1=interrupt request 2 has slave, 0=no slave +|   3   |1=interrupt request 3 has slave\\ 0=no slave| 
- | | | | `------- 1=interrupt request 3 has slave, 0=no slave +|   4   |1=interrupt request 4 has slave\\ 0=no slave| 
- | | | `-------- 1=interrupt request 4 has slave, 0=no slave +|   5   |1=interrupt request 5 has slave\\ 0=no slave| 
- | | `--------- 1=interrupt request 5 has slave, 0=no slave +|   6   |1=interrupt request 6 has slave\\ 0=no slave| 
- | `---------- 1=interrupt request 6 has slave, 0=no slave +|   7   |1=interrupt request 7 has slave\\ 0=no slave| 
- `----------- 1=interrupt request 7 has slave, 0=no slave + 
-</code> +^  bit  ^ Initialization Command Word 3 for Master Device^ 
-<code> +|  0-2  | master interrupt request slave is attached to  | 
-|7|6|5|4|3|2|1|0|  ICW3 for Slave Device +|  3-7  | must be zero| 
- | | | | | `-------- master interrupt request slave is attached to +
- `----------------- must be zero +
-</code>+
 ==== Initialization Command Word 4 at Port 21h and A1h ==== ==== Initialization Command Word 4 at Port 21h and A1h ====
-<code> +^  Bit  ^ Initialization Command Word 4                      ^ 
-|7|6|5|4|3|2|1|0|  ICW4 +|   0   | 1 for 80x86 mode\\ 0 = MCS 80/85 mode| 
- | | | | | | | `---- 1 for 80x86 mode, 0 = MCS 80/85 mode +|   1   | 1 = auto EOI\\ 0=normal EOI| 
- | | | | | | `----- 1 = auto EOI, 0=normal EOI +|  2-3  | slave/master buffered mode (see below)| 
- | | | | `-------- slave/master buffered mode (see below) +|   4   | 1 = special fully nested mode (SFNM)\\ 0=sequential| 
- | | | `--------- 1 = special fully nested mode (SFNM), 0=sequential +|  5-7  | unused (set to zero)|
- `-------------- unused (set to zero) +
-</code>+
  
 ^  Bits       |^ Buffering Mode                  ^ ^  Bits       |^ Buffering Mode                  ^
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 ==== Operation Control Word 1 / Interrupt Mask Reg. (Ports 21h & A1h) ==== ==== Operation Control Word 1 / Interrupt Mask Reg. (Ports 21h & A1h) ====
-<code> + 
-|7|6|5|4|3|2|1|0|  OCW1 - IMR Interrupt Mask Register +^  bit  ^ Operation Control Word 1 - IMR Interrupt Mask Register^ 
- | | | | | | | `---- 0 = service IRQ0, 1 = mask off +|   0   | 0 = service IRQ0\\ 1 = mask off| 
- | | | | | | `----- 0 = service IRQ1, 1 = mask off +|   1   | 0 = service IRQ1\\ 1 = mask off| 
- | | | | | `------ 0 = service IRQ2, 1 = mask off +|   2   | 0 = service IRQ2\\ 1 = mask off| 
- | | | | `------- 0 = service IRQ3, 1 = mask off +|   3   | 0 = service IRQ3\\ 1 = mask off| 
- | | | `-------- 0 = service IRQ4, 1 = mask off +|   4   | 0 = service IRQ4\\ 1 = mask off| 
- | | `--------- 0 = service IRQ5, 1 = mask off +|   5   | 0 = service IRQ5\\ 1 = mask off| 
- | `---------- 0 = service IRQ6, 1 = mask off +|   6   | 0 = service IRQ6\\ 1 = mask off| 
- `----------- 0 = service IRQ7, 1 = mask off +|   7   | 0 = service IRQ7\\ 1 = mask off|
- </code>+
  
 ==== Operation Control Word 2 / Interrupt Command Reg. (Ports 20h & A0h) ==== ==== Operation Control Word 2 / Interrupt Command Reg. (Ports 20h & A0h) ====
-<code> + 
-|7|6|5|4|3|2|1|0|  OCW2 - ICR Interrupt Command Register +^  bit  ^ Operation Control Word 2 - ICR Interrupt Command Register^ 
- | | | | | `-------- interrupt request level to act upon +|  0-2  | interrupt request level to act upon| 
- | | | | `--------- must be 0 for OCW2 +|   3   | must be 0 for OCW2| 
- | | | `---------- must be 0 for OCW2 +|   4   | must be 0 for OCW2| 
- `--------------- EOI type (see table) +|  5-7  | EOI type (see table)| 
-</code>+
  
 ^  Bits            ||^ EOI - End Of Interrupt code (PC specific)  ^ ^  Bits            ||^ EOI - End Of Interrupt code (PC specific)  ^
Ligne 86: Ligne 80:
 |  1     |  1  |  1  | rotate on specific EOI command             | |  1     |  1  |  1  | rotate on specific EOI command             |
  
-==== Operation Control Word 3   (Ports 20h & A0h) ==== +==== Operation Control Word 3 (Ports 20h & A0h) ==== 
-<code> +^  bit  ^ Operation Control Word 3 ^ 
-|7|6|5|4|3|2|1|0|  OCW3 +|   0  | 1=read IRR on next read\\ 0=read ISR on next read| 
- | | | | | | | `--- 1=read IRR on next read, 0=read ISR on next read +|   1  | 1=act on value of bit 0\\ 0=no action if bit 0 set| 
- | | | | | | `---- 1=act on value of bit 0, 0=no action if bit 0 set +|   2  | 1=poll command issued\\ 0=no poll command issued| 
- | | | | | `----- 1=poll command issued, 0=no poll command issued +|   3  | must be 1 for OCW3| 
- | | | | `------ must be 1 for OCW3 +|   4  | must be 0 for OCW3| 
- | | | `------- must be 0 for OCW3 +|   5  | 1=set special mask\\ 0=reset special mask| 
- | | `-------- 1=set special mask, 0=reset special mask +|   6  | 1=act on value of bit 5\\ 0=no action if bit 5 set| 
- | `--------- 1=act on value of bit 5, 0=no action if bit 5 set +|   7  | not used (zero)| 
- `---------- not used (zero) +
-</code>+
 ==== Other Registers ==== ==== Other Registers ====
  
-IRR - Interrupt Request Register, maintains a bit vector indicating which IRQ hardware events are awaiting service. Highest level interrupt is reset when the CPU acknowledges interrupt. +  * IRR - Interrupt Request Register, maintains a bit vector indicating which IRQ hardware events are awaiting service. Highest level interrupt is reset when the CPU acknowledges interrupt. 
-ISR - In Service Register, tracks IRQ line currently being serviced.  +  * ISR - In Service Register, tracks IRQ line currently being serviced. \\ Updated by EOI command.
-<tab>Updated by EOI command.+
  
-===== Hardware Interrupt Sequence of Events: ======+====== Hardware Interrupt Sequence of Events ======
  
   - 8259 <A HREF="int_table.html">IRQ</A> signal is raised high by hardware setting the corresponding IRR bits true.   - 8259 <A HREF="int_table.html">IRQ</A> signal is raised high by hardware setting the corresponding IRR bits true.
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 ==== Initialization ==== ==== Initialization ====
 +
   - write ICW1 to port 20h   - write ICW1 to port 20h
   - write ICW2 to port 21h   - write ICW2 to port 21h
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   - for a more in-depth discussion of the 8259, see Intel's "Micro-processor and Peripherals Handbook, Volume I"   - for a more in-depth discussion of the 8259, see Intel's "Micro-processor and Peripherals Handbook, Volume I"
  
-  - see  <A HREF="ports.html">PORTS</A>  and  <A HREF="int_table.html">INT TABLE</A> +<WRAP rounded box> 
 +see [[back2root:ibm-pc-ms-dos:hardware:start|PORTS]] and [[back2root:ibm-pc-ms-dos:interrupts:start|INT TABLE]] 
 +</WRAP>
back2root/ibm-pc-ms-dos/hardware/8259.1672278974.txt.gz · Dernière modification : 2022/12/29 02:56 de frater

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