Ceci est une ancienne révision du document !
|7|6|5|4|3|2|1|0| ICW1 | | | | | | | `---- 1=ICW4 is needed, 0=no ICW4 needed | | | | | | `----- 1=single 8259, 0=cascading 8259's | | | | | `------ 1=4 byte interrupt vectors, 0=8 byte int vectors | | | | `------- 1=level triggered mode, 0=edge triggered mode | | | `-------- must be 1 for ICW1 (port must also be 20h or A0h) `------------- must be zero for PC systems
|7|6|5|4|3|2|1|0| ICW2 | | | | | `-------- 000= on 80x86 systems `----------------- A7-A3 of 80x86 interrupt vector
|7|6|5|4|3|2|1|0| ICW3 for Master Device | | | | | | | `---- 1=interrupt request 0 has slave, 0=no slave | | | | | | `----- 1=interrupt request 1 has slave, 0=no slave | | | | | `------ 1=interrupt request 2 has slave, 0=no slave | | | | `------- 1=interrupt request 3 has slave, 0=no slave | | | `-------- 1=interrupt request 4 has slave, 0=no slave | | `--------- 1=interrupt request 5 has slave, 0=no slave | `---------- 1=interrupt request 6 has slave, 0=no slave `----------- 1=interrupt request 7 has slave, 0=no slave
|7|6|5|4|3|2|1|0| ICW3 for Slave Device | | | | | `-------- master interrupt request slave is attached to `----------------- must be zero
|7|6|5|4|3|2|1|0| ICW4 | | | | | | | `---- 1 for 80x86 mode, 0 = MCS 80/85 mode | | | | | | `----- 1 = auto EOI, 0=normal EOI | | | | `-------- slave/master buffered mode (see below) | | | `--------- 1 = special fully nested mode (SFNM), 0=sequential `-------------- unused (set to zero)
Bits | ||
---|---|---|
3 | 2 | Buffering Mode |
0 | 0 | not buffered |
0 | 1 | not buffered |
1 | 0 | buffered mode slave (PC mode) |
1 | 1 | buffered mode master (PC mode) |
|7|6|5|4|3|2|1|0| OCW1 - IMR Interrupt Mask Register | | | | | | | `---- 0 = service IRQ0, 1 = mask off | | | | | | `----- 0 = service IRQ1, 1 = mask off | | | | | `------ 0 = service IRQ2, 1 = mask off | | | | `------- 0 = service IRQ3, 1 = mask off | | | `-------- 0 = service IRQ4, 1 = mask off | | `--------- 0 = service IRQ5, 1 = mask off | `---------- 0 = service IRQ6, 1 = mask off `----------- 0 = service IRQ7, 1 = mask off
|7|6|5|4|3|2|1|0| OCW2 - ICR Interrupt Command Register | | | | | `-------- interrupt request level to act upon | | | | `--------- must be 0 for OCW2 | | | `---------- must be 0 for OCW2 `--------------- EOI type (see table)
Bits | |||
---|---|---|---|
7 | 6 | 5 | EOI - End Of Interrupt code (PC specific) |
0 | 0 | 1 | non-specific EOI command |
0 | 1 | 0 | NOP |
0 | 1 | 1 | specific EOI command |
1 | 0 | 0 | rotate in automatic EOI mode |
1 | 0 | 1 | rotate on non-specific EOI command |
1 | 1 | 0 | set priority command (uses bits 2-0) |
1 | 1 | 1 | rotate on specific EOI command |
|7|6|5|4|3|2|1|0| OCW3 | | | | | | | `--- 1=read IRR on next read, 0=read ISR on next read | | | | | | `---- 1=act on value of bit 0, 0=no action if bit 0 set | | | | | `----- 1=poll command issued, 0=no poll command issued | | | | `------ must be 1 for OCW3 | | | `------- must be 0 for OCW3 | | `-------- 1=set special mask, 0=reset special mask | `--------- 1=act on value of bit 5, 0=no action if bit 5 set `---------- not used (zero)
IRR - Interrupt Request Register, maintains a bit vector indicating which IRQ hardware events are awaiting service. Highest level interrupt is reset when the CPU acknowledges interrupt. ISR - In Service Register, tracks IRQ line currently being serviced. Updated by EOI command.