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back2root:ibm-pc-ms-dos:hardware:8259 [2022/12/29 02:55] – [Tableau] frater | back2root:ibm-pc-ms-dos:hardware:8259 [2023/01/16 16:33] (Version actuelle) – [8259 Programmable Interrupt Controller Notes] frater | ||
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Ligne 1: | Ligne 1: | ||
+ | ~~TOC 1-4 ~~ | ||
+ | |||
====== 8259 - Programmable Interrupt Controller (PIC) ====== | ====== 8259 - Programmable Interrupt Controller (PIC) ====== | ||
==== Initialization Command Word 1 at Port 20h and A0h ==== | ==== Initialization Command Word 1 at Port 20h and A0h ==== | ||
- | < | + | ^ Bit ^ Initialization Command Word 1 ^ |
- | |7|6|5|4|3|2|1|0| | + | | 0 | 1=ICW4 is needed\\ |
- | | | | | | | | `---- 1=ICW4 is needed, 0=no ICW4 needed | + | | |
- | | | | | | | `----- | + | | |
- | | | | | | `------ | + | | |
- | | | | | `------- | + | | |
- | | | | `-------- | + | | 5-7 | must be zero for PC systems |
- | `------------- must be zero for PC systems | + | |
- | </ | + | |
==== Initialization Command Word 2 at Port 21h and A1h ==== | ==== Initialization Command Word 2 at Port 21h and A1h ==== | ||
- | < | + | ^ Bit ^ Initialization Command Word 2 ^ |
- | |7|6|5|4|3|2|1|0| ICW2 | + | | 0-2 | 000= on 80x86 systems| |
- | | | | | | `-------- | + | | 3-7 | A7-A3 of 80x86 interrupt vector| |
- | `----------------- A7-A3 of 80x86 interrupt vector | + | |
- | </ | + | |
==== Initialization Command Word 3 at Port 21h and A1h ==== | ==== Initialization Command Word 3 at Port 21h and A1h ==== | ||
- | < | + | ^ bit ^ Initialization Command Word 3 for Master Device^ |
- | |7|6|5|4|3|2|1|0| | + | | 0 |1=interrupt request 0 has slave\\ 0=no slave| |
- | | | | | | | | `---- 1=interrupt request 0 has slave, 0=no slave | + | | 1 |1=interrupt request 1 has slave\\ 0=no slave| |
- | | | | | | | `----- | + | | 2 |1=interrupt request 2 has slave\\ 0=no slave| |
- | | | | | | `------ | + | | 3 |1=interrupt request 3 has slave\\ 0=no slave| |
- | | | | | `------- | + | | 4 |1=interrupt request 4 has slave\\ 0=no slave| |
- | | | | `-------- | + | | 5 |1=interrupt request 5 has slave\\ 0=no slave| |
- | | | `--------- | + | | 6 |1=interrupt request 6 has slave\\ 0=no slave| |
- | | + | | |
- | `----------- | + | |
- | </ | + | ^ bit ^ Initialization Command Word 3 for Master |
- | < | + | | |
- | |7|6|5|4|3|2|1|0| | + | | 3-7 | must be zero| |
- | | | | | | `-------- | + | |
- | `----------------- must be zero | + | |
- | </ | + | |
==== Initialization Command Word 4 at Port 21h and A1h ==== | ==== Initialization Command Word 4 at Port 21h and A1h ==== | ||
- | < | + | ^ Bit ^ Initialization Command Word 4 ^ |
- | |7|6|5|4|3|2|1|0| | + | | |
- | | | | | | | | `---- 1 for 80x86 mode, 0 = MCS 80/85 mode | + | | 1 | 1 = auto EOI\\ 0=normal EOI| |
- | | | | | | | `----- | + | | |
- | | | | | `-------- | + | | 4 | 1 = special fully nested mode (SFNM)\\ 0=sequential| |
- | | | | `--------- | + | | 5-7 | unused (set to zero)| |
- | `-------------- unused (set to zero) | + | |
- | </ | + | |
^ Bits |^ Buffering Mode ^ | ^ Bits |^ Buffering Mode ^ | ||
Ligne 55: | Ligne 50: | ||
==== Operation Control Word 1 / Interrupt Mask Reg. (Ports 21h & A1h) ==== | ==== Operation Control Word 1 / Interrupt Mask Reg. (Ports 21h & A1h) ==== | ||
- | < | + | |
- | |7|6|5|4|3|2|1|0| OCW1 - IMR Interrupt Mask Register | + | ^ bit ^ Operation Control Word 1 - IMR Interrupt Mask Register^ |
- | | | | | | | | `---- 0 = service IRQ0, 1 = mask off | + | | 0 | 0 = service IRQ0\\ 1 = mask off| |
- | | | | | | | `----- | + | | 1 | 0 = service IRQ1\\ 1 = mask off| |
- | | | | | | `------ | + | | 2 | 0 = service IRQ2\\ 1 = mask off| |
- | | | | | `------- | + | | 3 | 0 = service IRQ3\\ 1 = mask off| |
- | | | | `-------- | + | | 4 | 0 = service IRQ4\\ 1 = mask off| |
- | | | `--------- | + | | 5 | 0 = service IRQ5\\ 1 = mask off| |
- | | + | | 6 |
- | `----------- | + | | |
- | </ | + | |
==== Operation Control Word 2 / Interrupt Command Reg. (Ports 20h & A0h) ==== | ==== Operation Control Word 2 / Interrupt Command Reg. (Ports 20h & A0h) ==== | ||
- | < | ||
- | |7|6|5|4|3|2|1|0| | ||
- | | | | | | `-------- interrupt request level to act upon | ||
- | | | | | `--------- must be 0 for OCW2 | ||
- | | | | `---------- must be 0 for OCW2 | ||
- | | ||
- | </ | ||
- | ^ | + | ^ |
- | ^ 7 | + | | 0-2 | interrupt request level to act upon| |
+ | | | ||
+ | | | ||
+ | | 5-7 | EOI type (see table)| | ||
+ | |||
+ | |||
+ | ^ Bits ||^ EOI - End Of Interrupt code (PC specific) | ||
+ | ^ 7 | ||
| 0 | | 0 | ||
| 0 | | 0 | ||
Ligne 86: | Ligne 80: | ||
| 1 | | 1 | ||
- | ==== Operation Control Word 3 | + | ==== Operation Control Word 3 (Ports 20h & A0h) ==== |
- | < | + | ^ bit ^ Operation Control Word 3 ^ |
- | |7|6|5|4|3|2|1|0| OCW3 | + | | |
- | | | | | | | | `--- 1=read IRR on next read, 0=read ISR on next read | + | | 1 |
- | | | | | | | `---- 1=act on value of bit 0, 0=no action if bit 0 set | + | | 2 |
- | | | | | | `----- | + | | 3 |
- | | | | | `------ | + | | 4 |
- | | | | `------- | + | | 5 |
- | | | `-------- | + | | 6 | 1=act on value of bit 5\\ 0=no action if bit 5 set| |
- | | + | | |
- | `---------- | + | |
- | </ | + | |
==== Other Registers ==== | ==== Other Registers ==== | ||
- | IRR - Interrupt Request Register, maintains a bit vector indicating which IRQ hardware events are awaiting service. Highest level interrupt is reset when the CPU acknowledges interrupt. | + | * IRR - Interrupt Request Register, maintains a bit vector indicating which IRQ hardware events are awaiting service. Highest level interrupt is reset when the CPU acknowledges interrupt. |
- | ISR - In Service Register, tracks IRQ line currently being serviced. | + | |
- | <tab>Updated by EOI command. | + | |
- | ===== Hardware Interrupt Sequence of Events: ====== | + | ====== Hardware Interrupt Sequence of Events ====== |
- 8259 <A HREF=" | - 8259 <A HREF=" | ||
Ligne 118: | Ligne 110: | ||
==== Initialization ==== | ==== Initialization ==== | ||
+ | |||
- write ICW1 to port 20h | - write ICW1 to port 20h | ||
- write ICW2 to port 21h | - write ICW2 to port 21h | ||
Ligne 136: | Ligne 129: | ||
- for a more in-depth discussion of the 8259, see Intel' | - for a more in-depth discussion of the 8259, see Intel' | ||
- | - see | + | <WRAP rounded box> |
+ | see [[back2root: | ||
+ | </WRAP> |