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back2root:ibm-pc-ms-dos:hardware:8255 [2024/03/03 21:42] – frater | back2root:ibm-pc-ms-dos:hardware:8255 [2024/08/27 14:49] (Version actuelle) – [Pin-out] frater | ||
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====== 8255 - Programmable Peripheral Interface - PPI (PC,XT, PCjr) ====== | ====== 8255 - Programmable Peripheral Interface - PPI (PC,XT, PCjr) ====== | ||
- | ==== 8042 Commands | + | <WRAP group> |
+ | <WRAP column 300px> | ||
+ | {{ : | ||
+ | {{ : | ||
+ | </ | ||
+ | <WRAP column *> | ||
+ | The Intel 8255 (or i8255) Programmable Peripheral Interface | ||
- | === Commands System Issues to Keyboard (write port 60h) === | + | The 8255 provides 24 parallel input/ |
- | ^ Command | + | The 8255 is a member of the MCS-85 family of chips, designed by Intel for use with their 8085 and 8086 microprocessors and their descendants. |
- | | | + | |
- | === Keyboard Responses to System (read port 60h) === | + | It was first available in a 40-pin DIP and later a 44-pin PLCC packages. |
+ | It found wide applicability in digital processing systems and was later cloned by other manufacturers. | ||
- | <WRAP round box> | + | The 82C55 is a CMOS version for higher speed and lower current consumption. |
+ | The functionality of the 8255 is now mostly embedded in larger VLSI processing chips as a sub-function. | ||
+ | |||
+ | A CMOS version of the 8255 is still being made by Renesas but mostly used to expand the I/O of microcontrollers, | ||
+ | |||
+ | This chip is present only on PC, PC-XT and PCJunior, for AT and later model (AT, PS/2), it was replaced by the [[back2root: | ||
+ | </ | ||
</ | </ | ||
- | see [[back2root: | ||
- | ===== 8042 - Speaker Controller & NMI (AT,PS/2) - Port 61h ===== | ||
- | This register can be Write and Read | ||
- | ^ bit ^ Description | + | ===== Pin-out ===== |
- | | 0 | PIT Channel 2 enabled (see [[back2root: | + | |
- | | 1 | Speaker Position\\ < | + | |
- | | 2 | | | + | |
- | | 3 | | | + | |
- | | 4 | | | + | |
- | | 5 | | | + | |
- | | 6 | | | + | |
- | | 7 | Reset Keyboard status (scan code readed) | + | |
- | === Speaker === | + | <WRAP group> |
+ | < | ||
+ | {{: | ||
+ | </ | ||
+ | <WRAP half column> | ||
+ | {{tablelayout? | ||
+ | ^ PA0 - PA7 | Pins of port A | | ||
+ | ^ PB0 - PB7 | Pins of port B | | ||
+ | ^ PC0 - PC7 | Pins of port C | | ||
+ | ^ D0 - D7 | Data pins for the transfer of data | | ||
+ | ^ RESET | Reset input | | ||
+ | ^ RD | Read input (inverted) | ||
+ | ^ WR | Write input (inverted) | ||
+ | ^ CS | Chip select (inverted) | ||
+ | ^ A0 - A1 | Address pins | | ||
+ | </ | ||
+ | </ | ||
- | ==== 8042 Status Register (port 64h read) ==== | + | It consists of 40 pins and operates in +5V regulated power supply. |
+ | Port C is further divided into two 4-bit ports i.e. port C lower and port C upper and port C can work in either BSR (bit set rest) mode or in mode 0 of input-output mode of 8255. | ||
- | ===== 8042 Commands Related to PC Systems | + | Port B can work in either mode 0 or in mode 1 of input-output mode. |
- | ^ Command | + | Port A can work either |
- | | 20h | Read Command Byte: current 8042 command byte is placed | + | |
- | <WRAP round box> | + | It has two control groups, control group A and control group B. Control group A consist of port A and port C upper. |
+ | Control group B consists of port C lower and port B. Depending upon the value if CS’, A1 and A0 we can select different ports in different modes as input-output function or BSR. | ||
- | </WRAP> | + | This is done by writing a suitable word in control register (control word D0-D7). |
+ | |||
+ | ===== PC / XT / Junior Mapping ===== | ||
+ | |||
+ | {{tablelayout? | ||
+ | ^ A0 ^ A1 ^ Selection | ||
+ | | 0 | ||
+ | | 0 | ||
+ | | 1 | ||
+ | | 1 | ||
- | see <A HREF=" | ||