Ci-dessous, les différences entre deux révisions de la page.
Les deux révisions précédentesRévision précédenteProchaine révision | Révision précédente | ||
back2root:ibm-pc-ms-dos:hardware:8250 [2023/01/06 23:03] – [Port 3FD - Line Status Register - LSR (read only)] frater | back2root:ibm-pc-ms-dos:hardware:8250 [2023/02/23 20:55] (Version actuelle) – [UART - Universal Asynchronous Receiver/Transmitter] frater | ||
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- | ====== UART - Universal Asynchronous Receiver/ | + | ====== |
{{tablelayout? | {{tablelayout? | ||
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| 4-7 |reserved (zero) | | 4-7 |reserved (zero) | ||
- | + | <WRAP round box> | |
- | - 16550 will interrupt if data exists in the FIFO and isn't read within the time it takes to receive four bytes or if no data is received within the time it takes to receive four bytes. | + | |
+ | </ | ||
===== Baud Rate Divisor Table ===== | ===== Baud Rate Divisor Table ===== | ||
{{tablelayout? | {{tablelayout? | ||
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<WRAP round box> | <WRAP round box> | ||
- | - Bit 0 is set when a byte is placed in the Receiver Buffer Register and cleared when the byte is read by the CPU (or when the CPU clears the FIFO for the 16550). Results in Receive Data Available Interrupts if enabled. | + | * Bit 0 is set when a byte is placed in the Receiver Buffer Register and cleared when the byte is read by the CPU (or when the CPU clears the FIFO for the 16550). Results in Receive Data Available Interrupts if enabled. |
- | - Bits 1-4 indicate errors and result in Line Status Interrupts if enabled. | + | |
- | - Bit 1 is set when a second byte is received before the byte in the Receiver Buffer Register is read by the CPU (the 16550 in FIFO mode sets this bit when the queue is full and the byte in the Receiver Shift Register hasn't been moved into the queue). This bit is reset when the CPU reads the LSR | + | |
- | - Bit 2 is set whenever a byte is received that doesn' | + | |
- | - Bit 3 is set when a character is received without proper stop bits. Upon detecting a framing error the UART attempts to resynchronize. | + | |
- | - Bit 4 is set when a break condition is sensed (when space is detected for longer than 1 fullword). | + | |
- | - Bit 5 is set when the Transmit Holding Register shifts a byte into the Transmit Shift Register (or XMIT FIFO queue is empty for 16550) and is cleared when a byte is written to the THR (or the XMIT FIFO). Results in Transmit Holding Register Empty interrupts | + | |
- | - Bit 6 is set when both the Transmitter Holding Register and the Transmitter Shift Register are empty. On the 16550, when the XMIT FIFO and Transmitter Shift Register are empty. | + | |
- | - Bit 7 is 16550 specific and indicates there is a byte in the FIFO queue that was received with a Parity, Framing or Break error. | + | |
</ | </ | ||
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===== Port 3FE - Modem Status Register - MSR (read only) ===== | ===== Port 3FE - Modem Status Register - MSR (read only) ===== | ||
- | |7|6|5|4|3|2|1|0| | + | ^ bit ^2FE, 3FE Modem Status Register |
- | | | | | | | | `---- 1 = DCTS Delta CTS (CTS changed) | + | | 0 |1 = DCTS Delta CTS (CTS changed) |
- | | | | | | | `----- | + | | 1 |1 = DDSR Delta DSR (DSR changed)| |
- | | | | | | `------ | + | | 2 |1 = RI ring indicator changed| |
- | | | | | `------- | + | | 3 |1 = DDCD Delta Data Carrier Detect (DCD changed)| |
- | | | | `-------- | + | | 4 |1 = CTS| |
- | | | `--------- | + | | 5 |1 = DSR| |
- | | + | | 6 |1 = ring indicator (RI)| |
- | `----------- | + | | |
- | + | ||
- | - Bits 0-3 are reset when the CPU reads the MSR | + | |
- | - Bit 4 is the Modem Control Register RTS during loopback test | + | |
- | - Bit 5 is the Modem Control Register DTR during loopback test | + | |
- | - Bit 6 is the Modem Control Register OUT1 during loopback test | + | |
- | - Bit 7 is the Modem Control Register OUT2 during loopback test | + | |
+ | <WRAP round box> | ||
+ | * Bits 0-3 are reset when the CPU reads the MSR | ||
+ | * Bit 4 is the Modem Control Register RTS during loopback test | ||
+ | * Bit 5 is the Modem Control Register DTR during loopback test | ||
+ | * Bit 6 is the Modem Control Register OUT1 during loopback test | ||
+ | * Bit 7 is the Modem Control Register OUT2 during loopback test | ||
+ | </ | ||
===== Port 3FF/2FF - Scratch Pad Register (read/ | ===== Port 3FF/2FF - Scratch Pad Register (read/ | ||
Programming considerations: | Programming considerations: | ||
- | - 8250' | + | |
- | - 16550' | + | <WRAP round box> |
- | - PCs are capable of 38.4Kb, while AT's are capable of 115.2Kb | + | * 8250' |
- | - receiver checks only the first stop bit of each character regardless of the number of stop bits specified | + | |
- | - Older 8250 and 16450 UARTs may lose THRE interrupt if the THRE and Receive Data (RD) or the Line Status (LS) interrupts occur simultaneously during a full duplex transmission. | + | |
- | + | | |
- | 1. Disable/ | + | |
- | | + | |
- | | + | |
+ | | ||
| | ||
- | - data loss can occur without overrun or framing errors if the interrupts are serviced too slowly | + | * data loss can occur without overrun or framing errors if the interrupts are serviced too slowly |
- | - reserved bits are usually set to zero. Code should NOT rely on this being the case since future enhancement may use these bits | + | |
- | - see INT TABLE or IRQ for interrupt assignments | + | </ |
- | - see PORTS for COMx port assignment (3F8, | + | |
+ | * see [[back2root: | ||
+ | * see [[back2root: | ||