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Ci-dessous, les différences entre deux révisions de la page.

--- back2root:ibm-pc-ms-dos:hardware:8250 [2023/01/06 22:53] – [Port 3FB - Line Control Register - LCR (read/write)] frater
+++ back2root:ibm-pc-ms-dos:hardware:8250 [2023/02/23 20:55] (Version actuelle) – [UART - Universal Asynchronous Receiver/Transmitter] frater
@@ Ligne 1: / Ligne 1: @@
-====== UART - Universal Asynchronous Receiver/Transmitter ======
+====== 8250 - UART - Universal Asynchronous Receiver/Transmitter ======
 {{tablelayout?rowsHeaderSource=Auto}}
@@ Ligne 26: / Ligne 26: @@
 |  4-7  |reserved (zero)  |
+<WRAP round box>
-- 16550 will interrupt if data exists in the FIFO and isn't read within the time it takes to receive four bytes or if no data is received within the time it takes to receive four bytes.
+  * 16550 will interrupt if data exists in the FIFO and isn't read within the time it takes to receive four bytes or if no data is received within the time it takes to receive four bytes.
+</WRAP>
 ===== Baud Rate Divisor Table =====
 {{tablelayout?rowsHeaderSource=Auto}}
@@ Ligne 104: / Ligne 105: @@
+{{tablelayout?rowsHeaderSource=Auto}}
+^  Bits\\ 10  ^ Word length bits      ^
+|  00         | 5 bits per character  |
+|  01         | 6 bits per character  |
+|  10         | 7 bits per character  |
+|  11         | 8 bits per character  |
-| Bits\\ 10 | Word length bits|
+<WRAP round box>
-| 00 | 5 bits per character  |
+  * stop bits = 1.5 for 5 bit words or 2 for 6, 7 or 8 bit words
-| 01 | 6 bits per character  |
+  * bit 7 changes the mode of registers 3F8 and 3F9.  If set these registers become the LSB and MSB of the baud rate divisor.\\ Otherwise 3F8 is the Transmit/Receive Buffer Register and 3F9 is the Interrupt Enable Register.
-| 10 | 7 bits per character  |
+</WRAP>
-| 11 | 8 bits per character  |
-- stop bits = 1.5 for 5 bit words or 2 for 6, 7 or 8 bit words
-- bit 7 changes the mode of registers 3F8 and 3F9.  If set these
-  registers become the LSB and MSB of the baud rate divisor.
-  Otherwise 3F8 is the Transmit/Receive Buffer Register and 3F9 is
-  the Interrupt Enable Register.
 ===== Port 3FC - Modem Control Register - MCR (read/write) =====
-|7|6|5|4|3|2|1|0|  2FC, 3FC  Modem Control Register
+^  bit  ^2FC, 3FC  Modem Control Register   ^
- | | | | | | | `---- 1 = activate DTR
+|   0   |1 = activate DTR|
- | | | | | | `----- 1 = activate RTS
+|   0   |1 = activate RTS|
- | | | | | `------ OUT1
+|   0   |OUT1|
- | | | | `------- OUT2
+|   0   |OUT2|
- | | | `-------- 0 = normal, 1 = loop back test
+|   0   |0 = normal, 1 = loop back test|
- `------------- reserved (zero)
+|  6-7  |reserved (zero)|
-- If bit 4 is set, data from the Transmit Shift Register is received
+<WRAP round box>
-  in the Receiver Shift Register.  The SOUT line is set to logic
+  * If bit 4 is set, data from the Transmit Shift Register is received in the Receiver Shift Register.  The SOUT line is set to logic high, the SIN line and control lines are disconnected. CTS, DSR, RI and CD inputs are disconnected.  DTR, RTS, OUT1 and OUT2 are then connected internally.
-  high, the SIN line and control lines are disconnected.   CTS, DSR,
+</WRAP>
-  RI and CD inputs are disconnected.  DTR, RTS, OUT1 and OUT2 are
-  then connected internally.
 ===== Port 3FD - Line Status Register - LSR (read only) =====
-|7|6|5|4|3|2|1|0|  2FD, 3FD Line Status Register
+^  bit   ^2FD, 3FD Line Status Register  ^
- | | | | | | | `---- 1 = data ready
+|  0   |1 = data ready|
- | | | | | | `----- 1 = overrun error (OE)
+|  1   |1 = overrun error (OE)|
- | | | | | `------ 1 = parity error (PE)
+|  2   |1 = parity error (PE)|
- | | | | `------- 1 = framing error (FE)
+|  3   |1 = framing error (FE)|
- | | | `-------- 1 = break interrupt  (BI)
+|  4   |1 = break interrupt  (BI)|
- | | `--------- 1 = transmitter holding register empty (THRE)
+|  5   |1 = transmitter holding register empty (THRE)|
- | `---------- 1 = transmitter shift register empty (TSRE)
+|  6   |1 = transmitter shift register empty (TSRE)|
- `----------- 1 = 16550 PE/FE/Break in FIFO queue, 0 for 8250 & 16450
+|  7   |1 = 16550 PE/FE/Break in FIFO queue, 0 for 8250 & 16450|
+<WRAP round box>
+  * Bit 0 is set when a byte is placed in the Receiver Buffer Register and cleared when the byte is read by the CPU (or when the CPU clears the FIFO for the 16550). Results in Receive Data Available Interrupts if enabled.
+  * Bits 1-4 indicate errors and result in Line Status Interrupts if enabled.
+  * Bit 1 is set when a second byte is received before the byte in the Receiver Buffer Register is read by the CPU (the 16550 in FIFO mode sets this bit when the queue is full and the byte in the Receiver Shift Register hasn't been moved into the queue). This bit is reset when the CPU reads the LSR
+  * Bit 2 is set whenever a byte is received that doesn't match the requested parity. Reset upon reading the LSR. (The 16550 maintains parity information with each byte and sets bit 2 only when the byte is at the top of the FIFO queue.)
+  * Bit 3 is set when a character is received without proper stop bits. Upon detecting a framing error the UART attempts to resynchronize.  Reset by reading the LSR.  (The 16550 maintains this information with each byte and sets bit 3 only when the byte  is at the top of the FIFO queue.)
+  * Bit 4 is set when a break condition is sensed (when space is detected for longer than 1 fullword).  A zero byte is placed in the Receiver Buffer Register (or 16550 FIFO).  Reset by reading the LSR.  (The 16550 maintains this information with each byte and sets bit 4 only when the byte is at the top of the FIFO queue.)
+  * Bit 5 is set when the Transmit Holding Register shifts a byte into the Transmit Shift Register (or XMIT FIFO queue is empty for 16550) and is cleared when a byte is written to the THR (or the XMIT FIFO).	Results in Transmit Holding Register Empty interrupts  if enabled.
+  * Bit 6 is set when both the Transmitter Holding Register and the Transmitter Shift Register are empty. On the 16550, when the XMIT FIFO and Transmitter Shift Register are empty.
+  * Bit 7 is 16550 specific and indicates there is a byte in the FIFO queue that was received with a Parity, Framing or Break error.
+</WRAP>
-- Bit 0 is set when a byte is placed in the Receiver Buffer Register and cleared when the byte is read by the CPU (or when the CPU clears the FIFO for the 16550). Results in Receive Data Available Interrupts if enabled.
-- Bits 1-4 indicate errors and result in Line Status Interrupts if enabled.
-- Bit 1 is set when a second byte is received before the byte in the Receiver Buffer Register is read by the CPU (the 16550 in FIFO mode sets this bit when the queue is full and the byte in the Receiver Shift Register hasn't been moved into the queue). This bit is reset when the CPU reads the LSR
-- Bit 2 is set whenever a byte is received that doesn't match the requested parity. Reset upon reading the LSR. (The 16550 maintains parity information with each byte and sets bit 2 only when the byte is at the top of the FIFO queue.)
-- Bit 3 is set when a character is received without proper stop bits. Upon detecting a framing error the UART attempts to resynchronize.  Reset by reading the LSR.  (The 16550 maintains this information with each byte and sets bit 3 only when the byte  is at the top of the FIFO queue.)
-- Bit 4 is set when a break condition is sensed (when space is detected for longer than 1 fullword).  A zero byte is placed in the Receiver Buffer Register (or 16550 FIFO).  Reset by reading the LSR.  (The 16550 maintains this information with each byte and sets bit 4 only when the byte is at the top of the FIFO queue.)
-- Bit 5 is set when the Transmit Holding Register shifts a byte into the Transmit Shift Register (or XMIT FIFO queue is empty for 16550) and is cleared when a byte is written to the THR (or the XMIT FIFO).	Results in Transmit Holding Register Empty interrupts  if enabled.
-- Bit 6 is set when both the Transmitter Holding Register and the Transmitter Shift Register are empty. On the 16550, when the XMIT FIFO and Transmitter Shift Register are empty.
-- Bit 7 is 16550 specific and indicates there is a byte in the FIFO queue that was received with a Parity, Framing or Break error.
 ===== Port 3FE - Modem Status Register - MSR (read only) =====
-|7|6|5|4|3|2|1|0|  2FE, 3FE Modem Status Register
+^  bit   ^2FE, 3FE Modem Status Register  ^
- | | | | | | | `---- 1 = DCTS  Delta CTS  (CTS changed)
+|   0   |1 = DCTS  Delta CTS  (CTS changed) |
- | | | | | | `----- 1 = DDSR  Delta DSR  (DSR changed)
+|   1   |1 = DDSR  Delta DSR  (DSR changed)|
- | | | | | `------ 1 = RI ring indicator changed
+|   2   |1 = RI ring indicator changed|
- | | | | `------- 1 = DDCD  Delta Data Carrier Detect (DCD changed)
+|   3   |1 = DDCD  Delta Data Carrier Detect (DCD changed)|
- | | | `-------- 1 = CTS
+|   4   |1 = CTS|
- | | `--------- 1 = DSR
+|   5   |1 = DSR|
- | `---------- 1 = ring indicator (RI)
+|   6   |1 = ring indicator (RI)|
- `----------- 1 = receive line signal detect
+|   7   |1 = receive line signal detect|
-- Bits 0-3 are reset when the CPU reads the MSR
-- Bit 4 is the Modem Control Register RTS during loopback test
-- Bit 5 is the Modem Control Register DTR during loopback test
-- Bit 6 is the Modem Control Register OUT1 during loopback test
-- Bit 7 is the Modem Control Register OUT2 during loopback test
+<WRAP round box>
+  * Bits 0-3 are reset when the CPU reads the MSR
+  * Bit 4 is the Modem Control Register RTS during loopback test
+  * Bit 5 is the Modem Control Register DTR during loopback test
+  * Bit 6 is the Modem Control Register OUT1 during loopback test
+  * Bit 7 is the Modem Control Register OUT2 during loopback test
+</WRAP>
 ===== Port 3FF/2FF - Scratch Pad Register (read/write) =====
 Programming considerations:
-- 8250's, 16450's are essentially identical to program
-- 16550's is pin and software compatible with the 16450 but has an internal FIFO queue that may be enabled/disabled by software
+<WRAP round box>
-- PCs are capable of 38.4Kb, while AT's are capable of 115.2Kb
+  * 8250's, 16450's are essentially identical to program
-- receiver checks only the first stop bit of each character regardless of the number of stop bits specified
+  * 16550's is pin and software compatible with the 16450 but has an internal FIFO queue that may be enabled/disabled by software
-- Older 8250 and 16450 UARTs may lose THRE interrupt if the THRE and Receive Data (RD) or the Line Status (LS) interrupts occur simultaneously during a full duplex transmission.  RD and LS have higher priority than THRE which causes the lower priority interrupt to be lost.  The following are 3 methods used to avoid this problem:
+  * PCs are capable of 38.4Kb, while AT's are capable of 115.2Kb
+  * receiver checks only the first stop bit of each character regardless of the number of stop bits specified
-. Disable/re-enable THRE interrupt via the IER after processing Receive Data & Line Status interrupts.
+  * Older 8250 and 16450 UARTs may lose THRE interrupt if the THRE and Receive Data (RD) or the Line Status (LS) interrupts occur simultaneously during a full duplex transmission.  RD and LS have higher priority than THRE which causes the lower priority interrupt to be lost.  The following are 3 methods used to avoid this problem:
-. While inside the RD and LS interrupt routines check the LSR THRE bit and set a flag that a THRE interrupt was waiting.
+    - Disable/re-enable THRE interrupt via the IER after processing Receive Data & Line Status interrupts.
-. Poll the LSR THRE bit instead of using the IRR.
+    - While inside the RD and LS interrupt routines check the LSR THRE bit and set a flag that a THRE interrupt was waiting.
+    - Poll the LSR THRE bit instead of using the IRR.
-- data loss can occur without overrun or framing errors if the interrupts are serviced too slowly
+  * data loss can occur without overrun or framing errors if the interrupts are serviced too slowly
-- reserved bits are usually set to zero.  Code should NOT rely on this being the case since future enhancement may use these bits
+  * reserved bits are usually set to zero.  Code should NOT rely on this being the case since future enhancement may use these bits
-- see  INT TABLE  or  IRQ  for interrupt assignments
+</WRAP>
-- see  PORTS   for COMx port assignment (3F8,2F8,3E8,2E8,3220...)
+  * see [[back2root:ibm-pc-ms-dos:hardware:informations:irq|INT TABLE]] or [[back2root:ibm-pc-ms-dos:hardware:IRQ|IRQ]] for interrupt assignments
+  * see [[back2root:ibm-pc-ms-dos:hardware:start|PORTS]] for COMx port assignment (3F8,2F8,3E8,2E8,3220...)

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