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back2root:ibm-pc-ms-dos:hardware:8042
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Ci-dessous, les différences entre deux révisions de la page.
| Les deux révisions précédentesRévision précédenteProchaine révision | Révision précédenteDernière révisionLes deux révisions suivantes | ||
| back2root:ibm-pc-ms-dos:hardware:8042 [2022/12/29 16:36] – [8042 - Keyboard Controller (AT,PS/2)] frater | back2root:ibm-pc-ms-dos:hardware:8042 [2022/12/29 17:32] – [8042 - Speaker Controller (AT,PS/2) - Port 61h] frater | ||
|---|---|---|---|
| Ligne 1: | Ligne 1: | ||
| - | ====== 8042 - Keyboard Controller (AT, | + | ====== 8042 - Keyboard Controller (AT,PS/2) ====== |
| - | ==== 8042 Commands & Responses ==== | + | ==== 8042 Commands & Responses |
| - | === Commands System Issues to Keyboard (via 8042 port 60h) === | + | === Commands System Issues to Keyboard (write port 60h) === |
| ^ Command | ^ Command | ||
| Ligne 41: | Ligne 41: | ||
| - | === Keyboard Responses to System (via 8042 port 60h) === | + | === Keyboard Responses to System (read port 60h) === |
| | 00h |Key Detection Error or Overrun Error for Scan Code Set 1, replaces last key in the keyboard buffer if the buffer is full. | | | 00h |Key Detection Error or Overrun Error for Scan Code Set 1, replaces last key in the keyboard buffer if the buffer is full. | | ||
| Ligne 60: | Ligne 60: | ||
| see [[back2root: | see [[back2root: | ||
| + | ===== 8042 - Speaker Controller & NMI (AT,PS/2) - Port 61h ===== | ||
| + | |||
| + | This register can be Write and Read | ||
| + | |||
| + | ^ bit ^ Description | ||
| + | | 0 | PIT Channel 2 enabled (see [[back2root: | ||
| + | | 1 | Speaker Position\\ < | ||
| + | | 2 | | | ||
| + | | 3 | | | ||
| + | | 4 | | | ||
| + | | 5 | | | ||
| + | | 6 | | | ||
| + | | 7 | Reset Keyboard status (scan code readed) | ||
| + | |||
| + | === Speaker === | ||
| + | The speaker itself has two possible positions, " | ||
| + | |||
| + | This position can be set through bit 1 of port 0x61 on the Keyboard Controller. | ||
| + | |||
| + | If this bit is set (=1), the speaker will move to the " | ||
| + | |||
| + | Moving in and out repeatedly produces audible tones if the speed of repetition (the frequency) is within the range the speaker can reproduce and the human ear can hear. Also, a single movement in or out makes a click sound because it's so fast. Thus, a frequency which is too low to be heard as a tone may be heard as a rattle or buzz. (In fact, any frequency produced by this system also produces higher frequencies; | ||
| ==== 8042 Status Register (port 64h read) ==== | ==== 8042 Status Register (port 64h read) ==== | ||
| Ligne 80: | Ligne 102: | ||
| ^ Command | ^ Command | ||
| - | | 20h | Read Command Byte: current 8042 command byte is placed in port 60h. | + | | 20h | Read Command Byte: current 8042 command byte is placed in port 60h.| |
| - | | 60h | Write 8042 Command Byte: next data byte written to port 60h is placed in 8042 command register. Format (see table 1) | | + | | 60h | Write 8042 Command Byte: next data byte written to port 60h is placed in 8042 command register. Format (see table 1)| |
| - | | A4h | Password Installed Test:\\ returned data can be read from port 60h;\\ < | + | | A4h | Password Installed Test:\\ returned data can be read from port 60h;\\ < |
| - | | A5h | Load Security: bytes written to port 60h will be read until a null (0) is found. | + | | A5h | Load Security: bytes written to port 60h will be read until a null (0) is found.| |
| - | | A6h | Enable Security: works only if a password is already loaded | + | | A6h | Enable Security: works only if a password is already loaded| |
| - | | A7h | Disable Auxiliary Interface: sets Bit 5 of command register stopping auxiliary I/O by driving the clock line low | | + | | A7h | Disable Auxiliary Interface: sets Bit 5 of command register stopping auxiliary I/O by driving the clock line low| |
| - | | A8h | Enable Auxiliary Interface: clears Bit 5 of command register | + | | A8h | Enable Auxiliary Interface: clears Bit 5 of command register| |
| | A9h | Auxiliary Interface Test: clock and data lines are tested; results placed at port 60h are listed below\\ < | | A9h | Auxiliary Interface Test: clock and data lines are tested; results placed at port 60h are listed below\\ < | ||
| - | | AAh | Self Test: diagnostic result placed at port 60h, 55h=OK | + | | AAh | Self Test: diagnostic result placed at port 60h, 55h=OK| |
| - | | ABh | Keyboard Interface Test:clock and data lines are tested; results placed at port 60h are listed above with command A9h | + | | ABh | Keyboard Interface Test:clock and data lines are tested; results placed at port 60h are listed above with command A9h| |
| - | | ACh | Diagnostic Dump: sends 16 bytes of 8042's RAM, current input port state, current output port state and 8042 program status word to port 60h in scan-code format. | + | | ACh | Diagnostic Dump: sends 16 bytes of 8042's RAM, current input port state, current output port state and 8042 program status word to port 60h in scan-code format.| |
| - | | ADh | Disable Keyboard Interface: sets Bit 4 of command register stopping keyboard I/O by driving the clock line low | | + | | ADh | Disable Keyboard Interface: sets Bit 4 of command register stopping keyboard I/O by driving the clock line low| |
| - | | AEh | Enable Keyboard Interface: clears Bit 4 of command register enabling keyboard interface. | + | | AEh | Enable Keyboard Interface: clears Bit 4 of command register enabling keyboard interface.| |
| - | | C0h | Read Input Port: data is read from its input port (which is inaccessible to the data bus) and written to output register at port 60h; \\ output register should be empty before call. (see Table 2) | + | | C0h | Read Input Port: data is read from its input port (which is inaccessible to the data bus) and written to output register at port 60h; \\ output register should be empty before call. (see Table 2)| |
| - | | C1h | Poll Input Port Low Bits: Bits 0-3 of port 1 placed in status Bits 4-7 | | + | | C1h | Poll Input Port Low Bits: Bits 0-3 of port 1 placed in status Bits 4-7| |
| - | | C2h | Poll Input Port High Bits: Bits 4-7 of port 1 placed in status Bits 4-7 | + | | C2h | Poll Input Port High Bits: Bits 4-7 of port 1 placed in status Bits 4-7| |
| - | | D0h | Read Output Port: data is read from 8042 output port (which is inaccessible to the data bus) and placed in output register; the output register should be empty. (see command D1 below) | + | | D0h | Read Output Port: data is read from 8042 output port (which is inaccessible to the data bus) and placed in output register; the output register should be empty. (see command D1 below)| |
| - | | D1h | Write Output Port: next byte written to port 60h is placed in the 8042 output port (which is inaccessible to the data bus) (see Table 3) | + | | D1h | Write Output Port: next byte written to port 60h is placed in the 8042 output port (which is inaccessible to the data bus) (see Table 3)| |
| - | | D2h | Write Keyboard Output Register: on PS/2 systems the next data byte written to port 60h input register is written to port 60h output register as if initiated by a device; invokes interrupt if enabled | + | | D2h | Write Keyboard Output Register: on PS/2 systems the next data byte written to port 60h input register is written to port 60h output register as if initiated by a device; invokes interrupt if enabled| |
| - | | D3h | Write Auxiliary Output Register: on PS/2 systems the next data byte written to port 60h input register is written to port 60h output register as if initiated by a device; invokes interrupt if enabled | + | | D3h | Write Auxiliary Output Register: on PS/2 systems the next data byte written to port 60h input register is written to port 60h output register as if initiated by a device; invokes interrupt if enabled| |
| - | | D4h | Write Auxiliary Device: on PS/2 systems the next data byte written to input register a port at 60h is sent to the auxiliary device | + | | D4h | Write Auxiliary Device: on PS/2 systems the next data byte written to input register a port at 60h is sent to the auxiliary device| |
| - | | E0h | Read Test Inputs: 8042 reads its T0 and T1 inputs; data is placed in output register; | + | | E0h | Read Test Inputs: 8042 reads its T0 and T1 inputs; data is placed in output register; |
| - | | Fxh | Pulse Output Port: Bits 0-3 of the 8042 output port can be pulsed low for 6 æs; Bits 0-3 of command indicate which Bits should be pulsed; 0=pulse, 1=don' | + | | Fxh | Pulse Output Port: Bits 0-3 of the 8042 output port can be pulsed low for 6 æs; Bits 0-3 of command indicate which Bits should be pulsed; 0=pulse, 1=don' |
| == Table 1 == | == Table 1 == | ||
back2root/ibm-pc-ms-dos/hardware/8042.txt · Dernière modification : 2023/01/05 03:12 de frater
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