8250 - UART - Universal Asynchronous Receiver/Transmitter

Port	Description
3F8h/2F8h	Transmit/Receive Buffer (read/write) Baud Rate Divisor LSB if bit 7 of LCR is set (read/write)
3F9h/2F9h	IER - Interrupt Enable Register (read/write) Baud Rate Divisor MSB if bit 7 of LCR is set (read/write)
3FAh/2FAh	IIR - Interrupt Identification Register (read only) FCR - 16550 FIFO Control Register (write only)
3FBh/2FBh	LCR - Line Control Register (read/write)
3FCh/2FCh	MCR - Modem Control Register (read/write)
3FDh/2FDh	LSR - Line Status Register (read only)
3FEh/2FEh	MSR - Modem Status Register (read only)
3FFh/2FFh	Scratch Pad Register (read/write)

Detailed UART Description

Port 3F8h	Transmit/Receive Buffer (read/write) Baud Rate Divisor LSB if bit 7 of LCR is set (read/write)
Port 3F9h	Interrupt Enable Register - IER (read/write) Baud Rate Divisor MSB if bit 7 of LCR is set (read/write)

2F9h, 3F9h : Interrupt Enable Register

bit	Interrupt Enable Register
0	1 = enable data available int (and 16550 Timeout)
1	1 = enable THRE interrupt
2	1 = enable lines status interrupt
3	1 = enable modem-status-change interrupt
4-7	reserved (zero)

16550 will interrupt if data exists in the FIFO and isn't read within the time it takes to receive four bytes or if no data is received within the time it takes to receive four bytes.

Baud Rate Divisor Table

Baud Rate	Baud Rate Divisor	Baud Rate	Baud Rate Divisor
50	900h	2400	30h
110	417h	3600	20h
150	300h	4800	18h
300	180h	7200	10h
600	C0h	9600	0Ch
1200	60h	19200	06h
1800	40h	38400	03h
2000	3Ah	115200	01h

- Baud rate divisors can be calculated by taking the oscillating frequency (1,843,200) and dividing by the quantity of the desired baud rate times the UART clocking factor (16). Use the following formula:

Port 3FA - Interrupt Identification Register - IIR (read only)

2FA, 3FA Interrupt ID Register

bit	Interrupt ID Register
0	1 = no int. pending, 0=int. pending
1-2	Interrupt Id bits (see below)
3	16550 1 = timeout int. pending, 0 for 8250/16450
4-5	reserved (zero)
6-7	16550 set to 1 if FIFO queues are enabled

Bits 21	Meaning	Priority	To reset
00	modem-status-change	lowest	read MSR
01	transmit-register-empty	low	read IIR / write THR
10	data-available	high	read rec buffer reg
11	line-status	highest	read LSR

interrupt pending flag uses reverse logic, 0 = pending, 1 = none
interrupt will occur if any of the line status bits are set
THRE bit is set when THRE register is emptied into the TSR

Port 3FA - 16550 FIFO Control Register - FCR (write only)

bit	2FA, 3FA FIFO Control Register
0	1 = enable clear XMIT and RCVR FIFO queues
1	1 = clear RCVR FIFO
2	1 = clear XMIT FIFO
3	1 = change RXRDY & TXRDY pins from mode 0 to mode 1
4-5	reserved (zero)
6-7	trigger level for RCVR FIFO interrupt

Bits 76	RCVR FIFO Trigger Level
00	1 byte
01	4 bytes
10	8 bytes
11	14 bytes

Bit 0 must be set in order to write to other FCR bits
Bit 1 when set to 1 the RCVR FIFO is cleared and this bit is reset.
The receiver shift register is not cleared.
Bit 2 when set to 1 the XMIT FIFO is cleared and this bit is reset.
The transmit shift register is not cleared.

Port 3FB - Line Control Register - LCR (read/write)

bit	2FB, 3FB Line Control Register
0-1	word length select bits (see below)
2	0 = 1 stop bit, 1 = 1.5 or 2 (see note)
3	0 = no parity, 1 = parity (PEN)
4	0 = odd parity, 1 = even (EPS)
5	0 = parity disabled, 1 = enabled
6	0 = turn break off, 1 = force spacing break state
7	1 = baud rate divisor (DLAB); 0 = RBR, THR or IER

Bits 10	Word length bits
00	5 bits per character
01	6 bits per character
10	7 bits per character
11	8 bits per character

stop bits = 1.5 for 5 bit words or 2 for 6, 7 or 8 bit words
bit 7 changes the mode of registers 3F8 and 3F9. If set these registers become the LSB and MSB of the baud rate divisor.
Otherwise 3F8 is the Transmit/Receive Buffer Register and 3F9 is the Interrupt Enable Register.

Port 3FC - Modem Control Register - MCR (read/write)

bit	2FC, 3FC Modem Control Register
0	1 = activate DTR
0	1 = activate RTS
0	OUT1
0	OUT2
0	0 = normal, 1 = loop back test
6-7	reserved (zero)

If bit 4 is set, data from the Transmit Shift Register is received in the Receiver Shift Register. The SOUT line is set to logic high, the SIN line and control lines are disconnected. CTS, DSR, RI and CD inputs are disconnected. DTR, RTS, OUT1 and OUT2 are then connected internally.

Port 3FD - Line Status Register - LSR (read only)

bit	2FD, 3FD Line Status Register
0	1 = data ready
1	1 = overrun error (OE)
2	1 = parity error (PE)
3	1 = framing error (FE)
4	1 = break interrupt (BI)
5	1 = transmitter holding register empty (THRE)
6	1 = transmitter shift register empty (TSRE)
7	1 = 16550 PE/FE/Break in FIFO queue, 0 for 8250 & 16450

Bit 0 is set when a byte is placed in the Receiver Buffer Register and cleared when the byte is read by the CPU (or when the CPU clears the FIFO for the 16550). Results in Receive Data Available Interrupts if enabled.
Bits 1-4 indicate errors and result in Line Status Interrupts if enabled.
Bit 1 is set when a second byte is received before the byte in the Receiver Buffer Register is read by the CPU (the 16550 in FIFO mode sets this bit when the queue is full and the byte in the Receiver Shift Register hasn't been moved into the queue). This bit is reset when the CPU reads the LSR
Bit 2 is set whenever a byte is received that doesn't match the requested parity. Reset upon reading the LSR. (The 16550 maintains parity information with each byte and sets bit 2 only when the byte is at the top of the FIFO queue.)
Bit 3 is set when a character is received without proper stop bits. Upon detecting a framing error the UART attempts to resynchronize. Reset by reading the LSR. (The 16550 maintains this information with each byte and sets bit 3 only when the byte is at the top of the FIFO queue.)
Bit 4 is set when a break condition is sensed (when space is detected for longer than 1 fullword). A zero byte is placed in the Receiver Buffer Register (or 16550 FIFO). Reset by reading the LSR. (The 16550 maintains this information with each byte and sets bit 4 only when the byte is at the top of the FIFO queue.)
Bit 5 is set when the Transmit Holding Register shifts a byte into the Transmit Shift Register (or XMIT FIFO queue is empty for 16550) and is cleared when a byte is written to the THR (or the XMIT FIFO). Results in Transmit Holding Register Empty interrupts if enabled.
Bit 6 is set when both the Transmitter Holding Register and the Transmitter Shift Register are empty. On the 16550, when the XMIT FIFO and Transmitter Shift Register are empty.
Bit 7 is 16550 specific and indicates there is a byte in the FIFO queue that was received with a Parity, Framing or Break error.

Port 3FE - Modem Status Register - MSR (read only)

bit	2FE, 3FE Modem Status Register
0	1 = DCTS Delta CTS (CTS changed)
1	1 = DDSR Delta DSR (DSR changed)
2	1 = RI ring indicator changed
3	1 = DDCD Delta Data Carrier Detect (DCD changed)
4	1 = CTS
5	1 = DSR
6	1 = ring indicator (RI)
7	1 = receive line signal detect

Bits 0-3 are reset when the CPU reads the MSR
Bit 4 is the Modem Control Register RTS during loopback test
Bit 5 is the Modem Control Register DTR during loopback test
Bit 6 is the Modem Control Register OUT1 during loopback test
Bit 7 is the Modem Control Register OUT2 during loopback test

Port 3FF/2FF - Scratch Pad Register (read/write)

Programming considerations:

8250's, 16450's are essentially identical to program
16550's is pin and software compatible with the 16450 but has an internal FIFO queue that may be enabled/disabled by software
PCs are capable of 38.4Kb, while AT's are capable of 115.2Kb
receiver checks only the first stop bit of each character regardless of the number of stop bits specified
Older 8250 and 16450 UARTs may lose THRE interrupt if the THRE and Receive Data (RD) or the Line Status (LS) interrupts occur simultaneously during a full duplex transmission. RD and LS have higher priority than THRE which causes the lower priority interrupt to be lost. The following are 3 methods used to avoid this problem:
1. Disable/re-enable THRE interrupt via the IER after processing Receive Data & Line Status interrupts.
2. While inside the RD and LS interrupt routines check the LSR THRE bit and set a flag that a THRE interrupt was waiting.
3. Poll the LSR THRE bit instead of using the IRR.

data loss can occur without overrun or framing errors if the interrupts are serviced too slowly
reserved bits are usually set to zero. Code should NOT rely on this being the case since future enhancement may use these bits

see INT TABLE or IRQ for interrupt assignments
see PORTS for COMx port assignment (3F8,2F8,3E8,2E8,3220…)